Native support for execution of get exponent, get mantisssa, and scale instructions within a graphics processing unit via reuse of fused multiply-add execution unit hardware logic

A method comprising:

• receiving a scale instruction at a floating point unit (FPU) of a shader execution unit of a graphics processing unit (GPU), wherein the scale instruction specifies a first source operand, a second source operand, and a destination operand represented in floating-point format;
• and
• executing the scale instruction on a fused multiply-add (FMA) execution unit of the FPU by:
• based on a determination the first source operand and the second source operand represent a special case of a plurality of special cases:
• bypassing a main data flow of the FMA execution unit;
• and
• setting the destination operand to a value corresponding to the special case;
• and
• based on a determination the first source operand and the second source operand do not represent any of the plurality of special cases, following the main data flow of the FMA execution unit, including:
• generating a temporary mantissa by extracting a mantissa portion from the first source operand;
• generating a temporary integer value by converting the second source operand to integer format;
• generating a temporary exponent by adding an exponent portion of the first source operand to the temporary integer value;
• and
• setting the destination operand by applying overflow/underflow logic and rounding logic of the FMA execution unit to the temporary mantissa and the temporary exponent.

A non-transitory computer-readable storage medium embodying a set of instructions, including a get mantissa instruction, specifying a first source operand and a destination operand represented in floating-point format and specifying a second source operand containing a plurality of control bits, which when executed by a floating point unit (FPU) of a shader execution unit of a graphics processing unit (GPU) cause the FPU to:

• execute the get mantissa instruction on a fused multiply-add (FMA) execution unit of the FPU by:
• based on a determination the first source operand represents a special case of a plurality of special cases:
• bypassing a main data flow of the FMA execution unit;
• and
• setting the destination operand to a value corresponding to the special case;
• and
• based on a determination the first source operand does not represent any of the plurality of special cases, following the main data flow of the FMA execution unit, including:
• setting a mantissa portion of the destination operand to a mantissa portion of the first source operand;
• selectively setting an exponent portion of the destination operand to a bias value or the bias value minus 1 based on a normalization interval encoded within the plurality of control bits and an unbiased exponent value of the first source operand;
• and
• selectively setting a sign portion of the destination operand based on a sign control encoded within the plurality of control bits.

A graphics processing unit (GPU) comprising:

• a fused multiply-add (FMA) processing unit operable to:
• receive an instruction, wherein the instruction specifies a source operand and a destination operand represented in floating-point format;
• and
• execute the instruction by:
• after a determination indicative of the source operand representing a special case of a plurality of special cases:
• bypassing a main data flow of the FMA processing unit;
• and
• setting the destination operand to a value corresponding to the special case;
• and
• after a determination indicative of the source operand not representing any of the plurality of special cases, following the main data flow of the FMA processing unit.