Loading patent…
AssigneeImagination Technologies Limited
InventorThomas Rose
Estimating the term…
A method of selecting, in hardware logic, an ith largest or a pth smallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the rth iteration, the method comprises: summing an (m−r)th bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the rth bit of the selected number is determined and output and additionally the (m−r−1)th bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m−r)th bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.
A method of selecting, in fixed function hardware circuitry, a number from a set of n m-bit numbers, wherein the selected number is either an ith largest or a pth smallest number from the set of n m-bit numbers, where i, p, m and n are integers, the method comprising a plurality of iterations and each of the iterations comprising:
A fixed function hardware circuit arranged to select an ith largest or pth smallest number from a set of n m-bit numbers, where i, p, m and n are integers, the fixed function hardware circuitry being arranged to operate iteratively and comprising:
Dependencies are inferred from the claim text.