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US 2024/0402947 A1Published application
Semiconductor memory device
AssigneeKioxia Corporation
InventorYoshikazu HARADA
Life of this patent
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Abstract
A semiconductor memory device includes a memory cell array and a control circuit configured to receive a first command set, reject a second command set related to a write operation or an erase operation, in a first time period of executing a first operation on the memory cell array in response to the first command set, receive a third command set related to a read operation in the first time period, and execute the read operation on the memory cell array in response to the third command set.
Claims20
A semiconductor memory device comprising:
- a first plane including a first memory cell array
- a second plane including a second memory cell array;
- and
- a control circuit configured to:
- receive a first command set related to the first plane,
- output a first signal indicating whether or not the first plane is ready for a read operation in a first time period of executing a first operation on the first plane in response to the first command set,
- output a second signal indicating whether or not the first plane is ready for an operation in the first time period, and
- output a ready/busy signal indicating whether or not the semiconductor memory device is ready for the operation in the first time period.
5 more elements
Dependencies are inferred from the claim text.