US 2024/0402909 A1 · INTERFACE LAYOUT FOR STACKED MEMORY ARCHITECTURES

Abstract

Methods, systems, and devices for an interface layout for stacked memory architectures are described. A memory interface block may interface a plurality of memory dies to a host controller. The memory interface block may include an interface block coupled with multiple memory dies, which may be stacked on the memory interface block using through-silicon-vias. The memory interface block may include controllers, datapath blocks, and interface blocks associated with each memory die. As such, the memory interface block may perform functions such as queueing, ECC, and performing row repair and column repair procedures. In some examples, a layout for the memory interface block may include pairing controllers for at least two memory devices, such that a pair of controllers may share a command port to a pair of memory dies. Further, the memory interface block may include interfaces to the host controller that are different from the interface to each memory die.

Claims20

Dependent claims

An apparatus, comprising:

a plurality of interface blocks, each of the plurality of interface blocks comprising a first port configured for communication of data with a host controller and a second port configured for communication of commands with the host controller;
a first set of controllers, each controller of the first set of controllers coupled with one of a first subset of the plurality of interface blocks;
a second set of controllers, each controller of the second set of controllers coupled with one of a second subset of the plurality of interface blocks;
and
a plurality of contact blocks, each of the plurality of contact blocks comprising a set of third ports configured for communication of data with a plurality of memory dies and a fourth port configured for communication of commands with the plurality of memory dies, wherein, for each of the plurality of contact blocks, each third port of the set of third ports is coupled with one of the first set of controllers or one of the second set of controllers, and each of the fourth ports are common to the one of the first set of controllers and the one of the second set of controllers.

2 more elements

An apparatus, comprising:

a first set of controllers, each respective controller of the first set of controllers coupled with a respective memory die of a first set of memory dies via a first data port and a command port of a respective interface block of a set of interface blocks;
a second set of controllers, each respective controller of the second set of controllers coupled with a respective memory die of a second set of memory dies via a second data port and the command port of the respective interface block;
and
a set of repair blocks, each respective repair block of the set of repair blocks configured to perform address swapping based on receiving repair data from a first set of fuses via the respective command port, the repair data associated with the first set of memory dies and a second set of fuses associated with the second set of memory dies, wherein each respective repair block of the set of repair blocks comprises a respective memory array for storing the repair data.

1 more element

A method, comprising:

receiving a set of parameters for a memory interface block, wherein the set of parameters comprises a quantity of memory dies, a memory size, or a combination thereof;
generating, based at least in part on the set of parameters, a layout for a host controller interface block comprising a plurality of interface blocks, each interface block comprising a first port configured for communication of data with a host controller and a second port configured for communication of commands with the host controller;
generating, based at least in part on the set of parameters, a layout for a section comprising a plurality of contact blocks, each of the plurality of contact blocks comprising a set of third ports configured for communication of data with a plurality of memory dies and a fourth port configured for communication of commands with the plurality of memory dies, wherein the set of third ports comprises a first subset of the set of third ports located in a first portion of the memory interface block and a second subset of the set of third ports located in a second portion of the memory interface block;
and
generating, based at least in part on the set of parameters, a layout for an intermediate block comprising a plurality of controllers and a plurality of datapath blocks between the host controller interface block and the memory interface block.

2 more elements

Dependencies are inferred from the claim text.

Interface layout for stacked memory architectures

Life of this patent

Interface layout for stacked memory architectures

Life of this patent

Abstract

Claims20