Design of Photonic Logic Gates Based on S-Matrix Optimization

A method, comprising:

• determining, via a first optimizer circuit, a plurality of target coefficients of a target S-matrix representation model of a photonic circuit, based on photonic input signals and target photonic output signals of the target S-matrix representation model;
• comparing, via a comparator circuit, the plurality of target coefficients with a plurality of device coefficients of a S-matrix representation model of the photonic circuit;
• and
• updating, in an iterative manner via a second optimizer circuit, the plurality of device coefficients based on the comparison to determine a final version of the plurality of device coefficients,
• wherein the photonic circuit is defined in accordance with the final version of the plurality of device coefficients.

A non-transitory computer-readable storage medium comprising stored instructions that, when executed by at least one processor of an emulator circuit, cause the at least one processor to:

• determine a plurality of target coefficients of a target S-matrix representation model of a photonic circuit, based on photonic input signals and target photonic output signals of the target S-matrix representation model;
• compare the plurality of target coefficients with a plurality of device coefficients of a S-matrix representation model of the photonic circuit;
• and
• update in an iterative manner the plurality of device coefficients based on the comparison to determine a final version of the plurality of device coefficients,
• wherein the photonic circuit is defined in accordance with the final version of the plurality of device coefficients obtained by the emulator circuit.