Adaptive analog partial sum accumulation technology for energy-efficient compute-in-memory

A semiconductor apparatus comprising:

• a digital to analog conversion (DAC) stage to generate analog input activation signals;
• a multiply-accumulate (MAC) computation stage coupled to the DAC stage, the MAC computation stage to generate output activation results based on the analog input activation signals and multi-bit weight data stored in the MAC computation stage;
• an analog integration stage coupled to the MAC computation stage, the analog integration stage to conduct partial sum accumulations on the output activation results;
• an analog to digital conversion (ADC) stage coupled to the analog integration stage, the ADC stage to generate digital computation results based on an output of the analog integration stage;
• and
• a controller to vary a number of cycles in the partial sum accumulations based on an overflow condition associated with one or more of the output activation results or the output of the analog integration stage.

A method comprising:

• generating, by a digital to analog conversion (DAC) stage, analog input activation signals;
• generating, by a multiply-accumulate (MAC) computation stage coupled to the DAC stage, output activation results based on the analog input activation signals and multi-bit weight data stored in the MAC computation stage;
• conducting, by an analog integration stage coupled to the MAC computation stage, partial sum accumulations on the output activation results;
• generating, by an analog to digital conversion (ADC) stage coupled to the analog integration stage, digital computation results based on an output of the analog integration stage;
• and
• varying, by a controller, a number of cycles in the partial sum accumulations based on an overflow condition associated with one or more of the output activation results or the output of the analog integration stage.