Timer circuit and method for providing adjustable frequency timing in a closed-loop control circuit
OwnerMattias Anderssoninventor
Life of this patent
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Abstract
A timer circuit is configured for providing adjustable frequency timing in a closed-loop control circuit. The timer circuit includes a period register, a counter, and a comparator. The period register is configured to hold a period value. The comparator is configured to determine when the counter reaches the period value. The timer circuit is configured to adjust the frequency by adjusting an increment controlling the counter.
Claims14
A timer circuit configured for providing adjustable frequency timing in a closed-loop control circuit, the timer circuit comprising:
- a period register configured to hold a period value;
- a counter;
- and
- a comparator configured to determine when the counter reaches the period value;
- wherein the timer circuit is configured to adjust the frequency by adjusting an increment controlling the counter.
A controller configured to vary a frequency of a control-loop, the controller comprising a timer circuit which comprises:
- a period register configured to hold a period value;
- a counter;
- and
- a comparator configured to determine when the counter reaches the period value;
- wherein the timer circuit is configured to adjust the frequency by adjusting an increment controlling the counter.
A method for providing adjustable frequency timing in a closed-loop control circuit, wherein the method comprises:
- increasing a counter based on an increment;
- and
- determining if the counter reaches a period value, wherein the frequency is adjusted by adjusting the increment.
Dependencies are inferred from the claim text.