Increasing digital power amplifier efficiency by reusing driver current

A differential digital power amplifier configured to drive an RFID antenna with a sinusoidal output current with an RFID frequency which differential digital power amplifier comprises:

• a digital control section configured to output digital wave-forming bits to a first group of driver blocks and a second group of driver blocks wherein each group of the first and second group of driver blocks comprises a number of N parallel driver blocks, wherein each group of the first and second group of driver blocks is configured to provide one common output contact for the RFID antenna, wherein each driver block of the first and second group of driver blocks comprises:
• a first level shifter and a second level shifter, configured to shift the voltage of a corresponding wave-forming bit of the digital wave-forming bits provided by the digital control section, and
• a first trumpet buffer connected to an output of the first level shifter, configured to provide at an output of the first trumpet buffer a driver current with the RFID frequency needed at a gate contact of a drain extended PMOS transistor configured to load/unload a gate-source capacitance of the drain extended PMOS transistor, and
• a second trumpet buffer connected to an output of the second level shifter, configured to provide at an output of the second trumpet buffer the driver current with the RFID frequency needed at a gate contact of a drain extended NMOS transistor configured to load/unload a gate-source capacitance of the drain extended NMOS transistor, and
• that the differential digital power amplifier comprises an internal power supply configured to provide the power for the driver block of the first and second group of driver blocks, which internal power supply comprises:
• a first source follower transistor, with its drain contact connected to a supply voltage contact of a supply voltage and its gate contact (18) connected via a first voltage source to a ground contact of the supply voltage, which first source follower transistor is configured to provide at its source contact a second trumpet buffer supply voltage configured to supply the second trumpet buffers and the second level shifter of the driver blocks, and
• a second source follower transistor with its drain contact connected to the ground contact of the supply voltage and its gate contact connected via a second voltage source to the supply voltage contact of the supply voltage, which second source follower transistor is configured to provide at its source contact a first trumped buffer supply voltage configured to supply the first trumpet buffers and the first level shifters of the driver blocks, and
• a switch between the source contact of the first source follower transistor and the source contact of the second source follower transistor configured to short circuit these source contacts configured to unload/load the gate-source capacitances of the drain extended PMOS transistors of the driver blocks of the first and second group of driver blocks with charge carriers configured to be used to load/unload the gate-source capacitances of the drain extended NMOS transistors of the driver blocks of the first and second group of driver blocks configured to reduce the driver current needed at the gate contacts of said PMOS transistors and NMOS transistors, which switch is configured to be closed for supply voltages higher than a minimum voltage or
• a passive diode or an active diode between the source contact of the first source follower transistor and the source contact of the second source follower transistor configured to short circuit these source contacts configured to unload/load the gate-source capacitances of the drain extended PMOS transistors of the driver blocks of the first and second group of driver blocks with charge carriers configured to be used to load/unload the gate-source capacitances of the drain extended NMOS transistors of the driver blocks of the first and second group of driver blocks configured to reduce the driver current needed at the gate contacts of said PMOS transistors and NMOS transistors, if the supply voltage is higher than a second minimum voltage.