Masking-based digital binary multiplier
AssigneeMicrosoft Technology Licensing, LLC
InventorMathew Kent HALL
Life of this patent
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Abstract
Embodiments of the present disclosure include systems and methods for providing masking-based digital binary multipliers. A digital binary multiplier may receive a first plurality of input bits and a second plurality of input bits. The digital binary multiplier may receive a control signal indicating a mode of operation in a plurality of modes of operation. The digital binary multiplier may generate a plurality of partial products based on the first plurality of input bits and the second plurality of input bits. The digital binary multiplier may, based on the control signal, mask a subset of the plurality of partial products. The digital binary multiplier may generate a plurality of output bits based on the plurality of partial products.
Claims20
A method, executable by a digital binary multiplier, the method comprising:
- receiving a first plurality of input bits and a second plurality of input bits;
- receiving a control signal indicating a mode of operation in a plurality of modes of operation;
- generating a plurality of partial products based on the first plurality of input bits and the second plurality of input bits;
- based on the control signal, masking a subset of the plurality of partial products;
- and
- generating a plurality of output bits based on the plurality of partial products.
A digital binary multiplier circuit comprising:
- a first circuit configured to receive a first plurality of input bits and a second plurality of input bits;
- a second circuit configured to receive a control signal indicating a mode of operation in a plurality of modes of operation;
- a third circuit configured to generate a plurality of partial products based on the first plurality of input bits and the second plurality of input bits;
- a fourth circuit configured to mask, based on the control signal, a subset of the plurality of partial products;
- and
- a fifth circuit configured to generate a plurality of output bits based on the plurality of partial products.
Dependencies are inferred from the claim text.