Scan Chain Analysis Using Predefined Capture Signature

A method, comprising:

• shifting, by a scan chain that includes a plurality of scan-enabled flip-flop circuits, a scan-chain pattern from an input port of a test interface of an integrated circuit to an output port of the test interface, wherein at least one of the plurality of scan-enabled flip-flop circuits fails to shift the scan-chain pattern;
• after the scan-chain pattern fails to be shifted to the output port, concurrently loading, by a plurality of scan signature circuits that are coupled to respective ones of a subset of the plurality of scan-enabled flip-flop circuits, a known scan-chain pattern to the subset of the scan-enabled flip-flop circuits;
• and
• shifting, by a functioning portion of the scan chain, at least a portion of the known scan-chain pattern to the output port.

A computer-readable, non-transitory storage medium having design information stored thereon, wherein the design information specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor manufacturing system that is configured to use the design information to produce the hardware integrated circuit according to the design information, and wherein the design information specifies that the hardware integrated circuit comprises:

• a plurality of circuit blocks;
• a plurality of scan-enabled flip-flop circuits, forming one or more scan chains across the plurality of circuit blocks, configured to shift a scan chain test signal from a test input interface to a test output interface;
• and
• a plurality of scan signature circuits, included in respective ones of a subset of the plurality of scan-enabled flip-flop circuits, and configured to concurrently load, in response to a particular signal, a known scan-chain pattern to the subset of the scan-enabled flip-flop circuits;
• and
• wherein the plurality of scan-enabled flip-flop circuits is further configured to sequentially output at least a portion of the known scan-chain pattern to the test output interface.