US 2024/0393391 A1Published application

System and method for detecting faults in integrated circuits

AssigneeNXP B.V.

InventorsJorge Ernesto Perez Chamorro, Vasudev Srinivasan, Andreas Lentz, Jean-Michel Cioranesco

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Abstract

A fault detection system includes a state register, an error detection code (EDC) register, logic circuitry, an EDC generator, and an EDC checker. The state and EDC registers store first reference data and first checksum data, respectively. The logic circuitry executes a logic function based on the first reference data to iteratively generate second reference data that is different from the first reference data, and updates the first reference data of the state register with the second reference data of one iteration. The EDC generator iteratively generates second checksum data based on the iteratively generated second reference data and updates the first checksum data of the EDC register with the second checksum data of one iteration. The EDC checker detects a fault in the IC based on the updated first reference data and the updated first checksum data.

Claims20

Dependent claims

An integrated circuit (IC), comprising:

a fault detection system that comprises:
a state register and an error detection code (EDC) register configured to operate in synchronization with a first clock signal and a second clock signal, and store first reference data and first checksum data, respectively;
logic circuitry that is coupled to the state register, and configured to execute a logic function based on the first reference data to iteratively generate second reference data that is different from the first reference data, and update the first reference data of the state register at a reference triggering edge of the first clock signal with the corresponding second reference data;
a first EDC generator that is coupled to the logic circuitry and the EDC register, and configured to iteratively generate second checksum data such that the second checksum data is generated for each iteration based on the second reference data generated for the corresponding iteration, and update the first checksum data of the EDC register at a reference triggering edge of the second clock signal with the corresponding second checksum data;
and
an EDC checker that is coupled to the state register and the EDC register, and configured to detect a fault in the IC based on the updated first reference data and the updated first checksum data.

3 more elements

A method, comprising:

storing, by a state register and an error detection code (EDC) register of a fault detection system, first reference data and first checksum data, respectively, wherein an operation of the state register is synchronous with a first clock signal and an operation of the EDC register is synchronous with a second clock signal;
executing, by logic circuitry of the fault detection system, a logic function based on the first reference data to iteratively generate second reference data that is different from the first reference data;
iteratively generating, by a first EDC generator of the fault detection system, second checksum data, wherein the second checksum data is generated for each iteration based on the second reference data generated for the corresponding iteration;
updating, by the logic circuitry, the first reference data of the state register at a reference triggering edge of the first clock signal with the corresponding second reference data;
updating, by the first EDC generator, the first checksum data of the EDC register at a reference triggering edge of the second clock signal with the corresponding second checksum data;
and
detecting, by an EDC checker of the fault detection system, a fault in the IC based on the updated first reference data and the updated first checksum data.

4 more elements

Dependencies are inferred from the claim text.