Superconductor-semiconductor circuit for readout of superconductor current-storage elements

A superconducting signal storage circuit comprising:

• a direct current single-flux-quantum converter for converting each of a plurality of electrical signals received from an input circuit to a single-flux-quantum;
• a detector integration loop for inducing an integrated first current proportional to the single-flux-quantum converted from the each of the plurality of the electrical signals received from the input circuit;
• a Josephson transmission line comprising a plurality of Josephson junctions for propagating the single-flux-quantum from the direct current single-flux-quantum converter to the detector integration loop;
• and
• a readout element for reading the induced integrated first current from the detector integration loop, wherein the readout element comprises:
• a first transistor for applying a second current to the integrated first current from the detector integration loop circuit to generate a third current;
• a second transistor for generating a fourth current, wherein the fourth current is substantially equal to the first current from the detector integration loop circuit;
• a cryotron switching element comprising a cryotron gate and a cryotron channel, wherein the cryotron switching element is positioned to receive the third current through the cryotron gate and a fifth current through the cryotron channel, wherein the cryotron switching element switches the cryotron gate and the cryotron channel from a superconducting state to a normal metal state at a threshold value of the third current, wherein the fifth current through the switched cryotron channel in the normal metal state induces a first voltage;
• a capacitor positioned to receive the fourth current from the second transistor and accumulate a charge equivalent to the received fourth current;
• a semiconductor element comprising a third transistor and a fourth transistor for inducing a second voltage, wherein the first voltage induced by the cryotron channel switches off the third and the fourth transistors, wherein the switched off the third and the fourth transistors induce the second voltage, wherein the induced second voltage switches off the fourth current to the capacitor;
• a fifth transistor coupled to the capacitor to provide an access line for reading the accumulated charge on the capacitor, wherein a third voltage opens the fifth transistor to transfer the accumulated charge on the capacitor to the access line as a readout signal;
• and
• a column bus coupled to the fifth transistor to receive the readout signal.

A superconducting signal storage circuit comprising:

• a first transistor for applying a first current to an integrated second current received from a transduction circuit, wherein the applying the first current to the integrated second current comprises adding the first current to the integrated second current to generate a third current;
• a second transistor for generating a fourth current, wherein the fourth current is substantially equal to the integrated second current;
• a cryotron switching element positioned to receive the third current through a cryotron gate and a fifth current through a cryotron channel, wherein the cryotron switching element switches the cryotron gate and the cryotron channel from a superconducting state to a normal metal state at a threshold value of the third current, wherein the fifth current through the switched cryotron channel in the normal metal state induces a first voltage;
• a capacitor positioned to receive the fourth current from the second transistor and accumulate a charge equivalent to the received fourth current;
• a semiconductor element comprising a third transistor and a fourth transistor for inducing a second voltage, wherein the first voltage induced by the switched cryotron channel switches off the third and the fourth transistors, wherein the switched off the third and the fourth transistors induce the second voltage, wherein the induced second voltage switches off the fourth current to the capacitor;
• a fifth transistor coupled to the capacitor to provide an access line for reading the accumulated charge on the capacitor, wherein a third voltage opens the fifth transistor to transfer the accumulated charge on the capacitor to the access line as a readout signal;
• and
• a column bus coupled to the fifth transistor to receive the readout signal.