Memory device with a transistor above vertically stacked memory cells

An integrated assembly, comprising:

• multiple stacks of vertically stacked electronic devices;
• and
• a transistor positioned above a stack of vertically stacked electronic devices of the multiple stacks of vertically stacked electronic devices,
• wherein the transistor comprises:
• a channel positioned on top of the stack of vertically stacked electronic devices;
• a first source/drain region on top of a first portion of the channel;
• a second source/drain region on top of a second portion of the channel;
• a gate that is part of an access line running through the integrated assembly, wherein a top surface of the gate is lower than a top surface of the first source/drain region and is lower than a top surface of the second source/drain region;
• and
• a gate dielectric that separates the gate from the channel.

A method, comprising:

• forming a silicon layer on a base layer;
• forming a doped layer on the silicon layer;
• activating dopants of the doped layer;
• forming a memory array comprising multiple stacks of vertically stacked memory cells;
• and
• forming multiple transistors positioned above the memory array,
• wherein each transistor is positioned above a respective stack of vertically stacked memory cells, of the multiple stacks of vertically stacked memory cells, and comprises:
• a channel positioned on top of the respective stack of vertically stacked memory cells;
• a first source/drain region on top of a first portion of the channel;
• a second source/drain region on top of a second portion of the channel;
• a gate having a top surface that is lower than a top surface of the first source/drain region and that is lower than a top surface of the second source/drain region;
• and
• a gate dielectric that separates the gate from the channel.