Semiconductor memory devices and methods of manufacturing thereof

A memory system, comprising:

• a memory array comprising a plurality of memory cells, each of the memory cells including a transistor coupled to a first capacitor and a second capacitor in series, respectively;
• and
• an authentication circuit operatively coupled to the memory array,
• wherein the authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells, and wherein the logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first capacitor or second capacitor.

A method for fabricating memory devices, comprising:

• forming a first word line (WL) that extends along a first lateral direction;
• forming a gate dielectric layer over the first WL;
• patterning a semiconductor layer disposed over the gate dielectric layer;
• forming a first conductive structure over the patterned semiconductor layer, wherein the first conductive structure extends along the first lateral direction to traverse across the patterned semiconductor layer, and further extends along a vertical direction;
• and
• forming a second conductive structure and third conductive structure over the patterned semiconductor layer, wherein the second and third conductive structures, disposed on a first side of the first conductive structure along a second lateral direction, each extend along the vertical direction.