Modelling and prediction of virtual quality control data incorporating area location in the production of memory devices

A method, comprising:

• fabricating a plurality of a wafer comprising multiple ones of an integrated circuit using a first set of processing parameters;
• creating a first virtual inline quality control data model for the fabrication of the wafer from inline quality control data of test samples of the wafer and post-fabrication test data of the test samples, both of the inline quality control data and post-fabrication test data including area information on which of a plurality of distinct areas of the wafer that individual ones of the integrated circuits are formed;
• interpolating virtual inline quality control data for the fabrication of the wafer using the first set of processing parameters from the first virtual inline quality control data model and the post-fabrication test data;
• creating a second virtual inline quality control data model for the fabrication of the wafer using the first set of processing parameters from the interpolated virtual inline quality control data and an inline data report for the fabrication of the wafer using the first set of processing parameters;
• interpolating virtual inline quality control data for the fabrication of the wafer using the first set of processing parameters from the second virtual inline quality control data model and the inline data report;
• based on the interpolated virtual inline quality control data for the fabrication of the wafer using the first set of processing parameters from the second virtual inline quality control data model and the inline data report, adjusting the first set of processing parameters;
• and
• fabricating the wafer using the adjusted first set of processing parameters.

A system, comprising:

• one or more processors, the one or more processors configured to:
• receive, from a fabrication facility, inline quality control data of test samples from manufacture of a plurality of examples of a wafer comprising multiple ones of an integrated circuit, the inline quality control data including area information on which of a plurality of distinct areas of the wafer that individual ones of the integrated circuits are formed;
• receive post-manufacturing test data of the test samples, the post-manufacturing test data of the test samples including the area information for the test samples;
• create a first virtual inline quality control data model for the manufacture of the wafer from the inline quality control data and the post-manufacturing test data, including the area information for the test samples for the inline quality control data and the post-manufacturing test data;
• interpolate virtual inline quality control data including the area information for the manufacture of the wafer from the first virtual inline quality control data model and the post-manufacturing test data;
• receive, from the fabrication facility, an inline data report for the manufacture of the wafer;
• create a second virtual inline quality control data model including the area information for the manufacture of the wafer from the interpolated virtual inline quality control data and the inline data report;
• and
• provide the second virtual inline quality control data model to the fabrication facility.