Signed extension carry-look-ahead for accumulator with bit width difference
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHaruki Mori, Hidehiro Fujiwara, Wei-Chang Zhao
Life of this patent
Estimating the term…
Abstract
A device and method of operating the device are disclosed. In one aspect, a device includes receive a first bit of first input data and a plurality of second bits of second input data. The processing circuit generates a first output bit of output data based on the first bit of the first input data and a first bit of the plurality of second bits of the second input data. The processing circuit generates a second output bit of the output data based on the first bit of the first input data, the first bit of the plurality of second bits, and a second bit of the plurality of second bits of the second input data.
Claims20
A device, comprising:
- a processing circuit configured to:
- receive a first bit of first input data and a plurality of second bits of second input data;
- generate a first output bit of output data based on the first bit of the first input data and a first bit of the plurality of second bits of the second input data;
- and
- generate a second output bit of the output data based on the first bit of the first input data, the first bit of the plurality of second bits, and a second bit of the plurality of second bits of the second input data.
A system, comprising:
- a first logic gate configured to generate an enable signal based on a first bit of first input data;
- a first circuit configured to:
- receive a first bit and a second bit of second input data;
- and
- generate a first intermediate signal and a second intermediate signal based on the first bit and the second bit of second input data;
- and
- a second circuit configured to:
- receive the enable signal, the first intermediate signal, and the second intermediate signal;
- and
- generate a first output bit of output data based on the enable signal, the first intermediate signal, and the second intermediate signal.
A method, comprising:
- receiving, by a processing circuit, a first bit of first input data and a plurality of second bits of second input data;
- generating, by the processing circuit, a first output bit of output data based on the first bit of the first input data and a first bit of the plurality of second bits of the second input data;
- and
- generating, by the processing circuit, a second output bit of the output data based on the first bit of the first input data, the first bit of the plurality of second bits, and a second bit of the plurality of second bits of the second input data.
Dependencies are inferred from the claim text.