Seal ring reinforcement
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYen Lian LAI, Chun Yu CHEN
Life of this patent
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Abstract
Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes an interconnect structure that includes a first metal line, a second metal line, a third metal line, a fourth metal line, and a fifth meal line extending along a first direction, a first group of lateral connectors disposed between the second metal line and the third metal line or between the fourth metal line and the fifth metal line, and a second group of lateral connectors disposed between the first metal line and the second metal line or between the third metal line and the fourth metal line.
Claims20
A method for forming an integrated circuit (IC) device, comprising:
- receiving a substrate comprising a device region and a ring region surrounding the device region;
- and
- repeating, for a number of times, a process cycle that includes:
- depositing a dielectric layer over the substrate, and
- forming, in the dielectric layer over the ring region:
- a first via bar ring extending continuously around the device region,
- a second via bar ring extending continuously around the device region,
- a plurality of metal line rings over the first via bar ring and the second via bar ring, and
- a plurality of lateral connectors interleaving the plurality of metal line rings.
A method, comprising:
- receiving a substrate comprising a device region and a ring region surrounding the device region;
- forming a first number of interconnect layers by repeating, for the first number of times, a first process cycle that includes:
- depositing a first dielectric layer over the substrate, and
- forming, in the first dielectric layer over the ring region:
- a first via bar ring extending continuously around the device region,
- a second via bar ring extending continuously around the device region,
- a first plurality of metal line rings over the first via bar ring and the second via bar ring, and
- a plurality of lateral connectors interleaving the first plurality of metal line rings;
- and
- after the forming of the first number of interconnect layers, forming a second number of interconnect layers by repeating, for the second number of times, a second process cycle that includes:
- depositing a second dielectric layer over the substrate, and
- forming, in the second dielectric layer over the ring region:
- a third via bar ring extending continuously around the device region,
- a fourth via bar ring extending continuously around the device region, and
- a second plurality of metal line rings over the first via bar ring and the second via bar ring.
A method, comprising:
- receiving a substrate comprising a device region and a ring region surrounding the device region;
- depositing a dielectric layer over the substrate;
- and
- forming, in the dielectric layer over the ring region:
- a first via bar ring,
- a second via bar ring,
- a plurality of metal line rings over the first via bar ring and the second via bar ring, and
- a plurality of lateral connectors interleaving the plurality of metal line rings,
- wherein the plurality of lateral connectors are aligned along a first direction.
Dependencies are inferred from the claim text.