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US 2024/0379446 A1Published application
Dual Dopant Source/Drain Regions and Methods of Forming Same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
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Abstract
A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.
Claims20
A method comprising:
- etching a recess in a semiconductor substrate, the recess being adjacent to a gate stack;
- forming a source/drain region in the recess, wherein forming the source/drain region comprises:
- epitaxially growing a first epitaxy material in the recess;
- performing a first implantation process to implant first impurities in the first epitaxy material;
- performing a second implantation process to implant second impurities in the first epitaxy material, wherein the first impurities have a lower formation enthalpy than the second impurities;
- performing an annealing process after the first implantation process and the second implantation process to define:
- a first doped region comprising the first impurities;
- and
- a second doped region comprising the second impurities, wherein the first impurities of the first doped region are disposed at a top surface of the semiconductor substrate and extend along sides of the second doped region.
6 more elements
A method comprising:
- etching a recess in a semiconductor substrate, the recess being adjacent to a gate stack;
- epitaxially growing a first epitaxy material in the recess;
- performing a first implantation process to implant arsenic in the first epitaxy material;
- after the first implantation process, performing a second implantation process to implant phosphorus in the first epitaxy material;
- after the second implantation process, performing an annealing process, wherein the annealing process defines:
- a first doped region comprising arsenic, the first doped region being at least partially disposed in the first epitaxy material;
- and
- a second doped region comprising phosphorous, the second doped region being at least partially disposed in the first epitaxy material, wherein the arsenic of the first doped region extend along sides of and below the second doped region.
5 more elements
A method comprising:
- forming a gate stack at a top surface of a semiconductor substrate;
- etching an opening adjacent to the gate stack;
- epitaxially growing a first epitaxy region in the opening, wherein the first epitaxy region is grown to a top surface of the semiconductor substrate;
- sequentially implanting first impurities and second impurities in the first epitaxy region, the first impurities having a lower formation enthalpy than the second impurities;
- performing an annealing process on the first epitaxy region to form a first doped region and a second doped region, the first doped region being doped with the first impurities, the second doped region doped with the second impurities, the first impurities of the first doped region extending along sides of the second impurities of the second doped region and below the second impurities of the second doped region;
- and
- forming a source/drain contact extending into the second doped region.
4 more elements
Dependencies are inferred from the claim text.