Convolution Calculation Engine Using Look-Up Tables for Address Calculation

A statically reconfigurable dataflow architecture processor comprising:

• an array of coarse-grained reconfigurable (CGR) units including a plurality of statically reconfigurable memory units, a plurality of statically reconfigurable compute units, a plurality of statically reconfigurable switches, and a plurality of links that respectively connect two of the CGR units, and respectively include a vector link;
• the plurality of statically reconfigurable compute units respectively including an array of multiply-accumulate circuits (MACs) having a plurality of lanes and a plurality of stages, the plurality of statically reconfigurable compute units including a first statically reconfigurable compute unit;
• the plurality of statically reconfigurable memory units respectively including a memory array, a general address calculation unit, and a convolution address compute unit, the plurality of statically reconfigurable memory units including a first, a second, and a third statically reconfigurable memory unit;
• and
• convolution address compute units of the plurality of statically reconfigurable memory units respectively comprising:
• a kernel element counter for a convolution operation between a kernel and an input tensor, the kernel element counter wrapping back to an initial kernel count value after reaching a maximum kernel count value;
• an offset look-up table (LUT) that provides a relative input offset into the input tensor based on an output of the kernel element counter;
• and
• input location calculation logic that provides an input location within an input tensor for the convolution operation based on the relative input offset provided by the offset LUT.