Etching back and selective deposition of metal gate
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPeng-Soon Lim, Cheng-Lung Hung, Mao-Lin Huang, Weng Chang
Life of this patent
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Abstract
A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.
Claims20
A device comprising:
- a first transistor comprising:
- a first semiconductor region;
- a first gate spacer over the first semiconductor region;
- and
- a first gate stack, wherein the first gate spacer is in contact with the first gate stack, and wherein the first gate stack comprises:
- a first gate dielectric;
- a first plurality of conductive layers over the first gate dielectric, wherein the first plurality of conductive layers are spaced apart from the first gate spacer by the first gate dielectric;
- and
- a first metallic layer over and contacting the first plurality of conductive layers;
- and
- a dielectric hard mask over and contacting the first metallic layer.
A device comprising:
- a semiconductor substrate;
- a plurality of shallow trench isolation regions in the semiconductor substrate;
- a semiconductor fin higher than top surfaces of the plurality of shallow trench isolation regions;
- a gate stack comprising:
- a high-k dielectric layer over the semiconductor fin;
- a plurality of first conductive layers over the high-k dielectric layer, the plurality of first conductive layers having U-shapes in a cross-section of the gate stack;
- and
- a second conductive layer over and contacting top surfaces of the plurality of first conductive layers;
- and
- a gate spacer comprising a first sidewall contacting a second sidewall of the gate stack, wherein the second conductive layer contacts one of the first sidewall of the gate spacer and a third sidewall of the high-k dielectric layer.
A device comprising:
- a semiconductor region;
- and
- a gate stack over the semiconductor region, wherein the gate stack comprises:
- a gate dielectric;
- and
- a gate electrode over the gate dielectric, the gate electrode comprising:
- a plurality of conductive layers comprising a work-function layer therein, wherein a topmost layer of the plurality of conductive layers has a U-shape in a cross-section of the gate stack, wherein the U-shape comprises a horizontal portion and two vertical portions over and joined to opposing ends of the horizontal portion;
- and
- a metallic layer over and contacting the plurality of conductive layers, wherein the metallic layer comprises:
- a middle part comprising a bottom portion in the U-shape;
- and
- opposite parts on opposite sides of the middle part, wherein the middle part has a same thickness as the opposite parts.
Dependencies are inferred from the claim text.