Amplifier with cascode arrangement

A unity gain buffer comprising:

• a first input terminal configured to receive a first input voltage;
• a non-inverting input terminal configured to receive a second input voltage, wherein the first input voltage tracks the second input voltage;
• a first voltage supply terminal configured to receive a first supply voltage;
• an output terminal configured to provide an output voltage;
• and
• a first cascode arrangement electrically coupled between the first voltage supply terminal and the output terminal, the first cascode arrangement comprising:
• a first transistor coupled to the output terminal and having a first gate terminal that is configured to receive a variable bias voltage, wherein the variable bias voltage corresponds to the first input voltage;
• and
• a second transistor coupled between the first transistor and the first voltage supply terminal and having a second gate terminal that is configured to receive a fixed bias voltage, wherein the first transistor is configured to prevent a voltage differential across the second transistor from exceeding a predefined voltage threshold.

Control circuitry comprising:

• an amplifier transistor configured to receive an RF input signal for amplification;
• a reference transistor, wherein the amplifier transistor and the reference transistor are formed on the same semiconductor die;
• a switch having an output coupled to a control terminal of the amplifier transistor;
• and
• a unity gain buffer comprising:
• an input terminal configured to receive a first input voltage;
• a non-inverting input terminal coupled to the reference transistor and configured to receive a second input voltage, wherein the first input voltage tracks the second input voltage;
• a voltage supply terminal configured to receive a supply voltage;
• an output terminal configured to provide an output voltage to the control terminal of the amplifier transistor via the switch;
• and
• a cascode arrangement electrically coupled between the voltage supply terminal and the output terminal, the cascode arrangement comprising:
• a first transistor coupled to the output terminal and having a first gate terminal that is configured to receive a variable bias voltage, wherein the variable bias voltage corresponds to the first input voltage;
• and
• a second transistor coupled between the first transistor and the voltage supply terminal and having a second gate terminal that is configured to receive a fixed bias voltage, wherein the first transistor is configured to prevent a voltage differential across the second transistor from exceeding a predefined voltage threshold.