Low latency serial bus
AssigneeTexas Instruments Incorporated
InventorsWin Naing MAUNG, Roy WOJCIECHOWSKI, James SKIDMORE
Life of this patent
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Abstract
A serial bus control circuit includes a link layer control circuit. The link layer control circuit is configured to control isochronous data transfer over a serial bus. The link layer control circuit includes an isochronous cycle timer configured to provide a cycle frame that is less than 125 microseconds in duration. The link layer control circuit can be configured to set the isochronous cycle timer to provide a cycle frame duration that produces an isochronous transfer latency of no more than 50 microseconds.
Claims20
A serial bus control circuit comprising:
- a link layer control circuit configured to control isochronous data transfer over a serial bus, the link layer control circuit including:
- an isochronous cycle timer configured to provide a cycle frame that is less than 125 microseconds in duration.
A method, comprising:
- setting an isochronous cycle timer to provide a cycle frame that is no more than 50 microseconds in duration;
- generating an isochronous packet;
- and
- transmitting the isochronous packet in the cycle frame.
An active noise cancellation (ANC) system, comprising:
- a microphone;
- a speaker;
- and
- an ANC controller coupled to the microphone and the speaker by a serial bus, in which the ANC controller includes a link layer control circuit configured to control isochronous data transfer between the ANC controller, the microphone, and the speaker over the serial bus, and the link layer control circuit includes an isochronous cycle timer configured to provide a cycle frame that is less than 125 microseconds in duration.
Dependencies are inferred from the claim text.