US 2024/0355833 A1 · SEMICONDUCTOR DEVICE

Abstract

A semiconductor device capable of stable operation with low power consumption is provided. A logic circuit having a circuit configuration using a transistor including an oxide semiconductor in a channel formation region is included. The logic circuit is a two-input/two-output two-wire logic circuit. Transistors included in the logic circuit each include a gate and a back gate. An input terminal is electrically connected to one of a gate and a back gate of a transistor electrically connected to a wiring for supplying a high power supply potential. An output terminal is connected to the other of the gate and the back gate of the transistor electrically connected to the wiring for supplying a high power supply potential. An output terminal is electrically connected to one of a source and a drain of a transistor electrically connected to a wiring for supplying a low power supply potential. A gate or a back gate of the transistor electrically connected to the wiring for supplying a low power supply potential is electrically connected to an input terminal.

Claims16

Dependent claims

(canceled)

A semiconductor device comprising:

first to eighth transistor;
a first wiring;
and
a second wiring,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first output terminal,
wherein a first gate of the first transistor is electrically connected to a first input terminal,
wherein a second gate of the first transistor is electrically connected to the first input terminal,
wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,
wherein a first gate of the second transistor is electrically connected to a second input terminal,
wherein a second gate of the second transistor is electrically connected to the second input terminal,
wherein one of a source and a drain of the third transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to a second output terminal,
wherein a first gate of the third transistor is electrically connected to a third input terminal,
wherein a second gate of the third transistor is electrically connected to the third input terminal,
wherein one of a source and a drain of the fourth transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the second output terminal,
wherein a first gate of the fourth transistor is electrically connected to a fourth input terminal,
wherein a second gate of the fourth transistor is electrically connected to the fourth input terminal,
wherein one of a source and a drain of the fifth transistor is electrically connected to the first output terminal,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the first wiring,
wherein a first gate of the fifth transistor is electrically connected to the third input terminal,
wherein a second gate of the fifth transistor is electrically connected to the first output terminal,
wherein one of a source and a drain of the sixth transistor is electrically connected to the first output terminal,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the first wiring,
wherein a first gate of the sixth transistor is electrically connected to the fourth input terminal,
wherein a second gate of the sixth transistor is electrically connected to the first output terminal,
wherein one of a source and a drain of the seventh transistor is electrically connected to the other of the source and the drain of the eighth transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the first wiring,
wherein a first gate of the seventh transistor is electrically connected to the first input terminal,
wherein a second gate of the seventh transistor is electrically connected to the second output terminal,
wherein one of a source and a drain of the eighth transistor is electrically connected to the second output terminal,
wherein a first gate of the eighth transistor is electrically connected to the second input terminal, and
wherein a second gate of the eighth transistor is electrically connected to the second output terminal.

31 more elements

A semiconductor device comprising:

a first input terminal and a second input terminal;
a first output terminal and a second output terminal;
a first wiring to a third wiring;
and
first to eighth transistors,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring, one of a gate and a back gate is electrically connected to the first input terminal, and the other of the source and the drain and the other of the gate and the back gate are electrically connected to a gate and a back gate of the second transistor,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring and the other of the source and the drain is electrically connected to the second output terminal,
wherein one of a source and a drain of the third transistor is electrically connected to the first wiring, one of a gate and a back gate is electrically connected to the second input terminal, and the other of the source and the drain and the other of the gate and the back gate are electrically connected to a gate and a back gate of the fourth transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the second wiring and the other of the source and the drain is electrically connected to the first output terminal,
wherein a gate and a back gate of the fifth transistor are electrically connected to the first input terminal, one of a source and a drain is electrically connected to the gate and the back gate of the fourth transistor, and the other of the source and the drain is electrically connected to the third wiring,
wherein a gate and a back gate of the sixth transistor are electrically connected to the first input terminal, one of a source and a drain is electrically connected to the first output terminal, and the other of the source and the drain is electrically connected to the third wiring,
wherein a gate and a back gate of the seventh transistor are electrically connected to the second input terminal, one of a source and a drain is electrically connected to the gate and the back gate of the second transistor, and the other of the source and the drain is electrically connected to the third wiring, and
wherein a gate and a back gate of the eighth transistor are electrically connected to the second input terminal, one of a source and a drain is electrically connected to the second output terminal, and the other of the source and the drain is electrically connected to the third wiring.

10 more elements

A semiconductor device comprising a plurality of switch circuits and a plurality of logic circuits,

wherein each logic circuit comprises:
a first input terminal and a second input terminal;
a first output terminal and a second output terminal;
a first wiring to a third wiring;
and
first to eighth transistors,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring, one of a gate and a back gate is electrically connected to the first input terminal, and the other of the source and the drain and the other of the gate and the back gate are electrically connected to a gate and a back gate of the second transistor,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring and the other of the source and the drain is electrically connected to the second output terminal,
wherein one of a source and a drain of the third transistor is electrically connected to the first wiring, one of a gate and a back gate is electrically connected to the second input terminal, and the other of the source and the drain and the other of the gate and the back gate are electrically connected to a gate and a back gate of the fourth transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the second wiring and the other of the source and the drain is electrically connected to the first output terminal,
wherein a gate and a back gate of the fifth transistor are electrically connected to the first input terminal, one of a source and a drain is electrically connected to the gate and the back gate of the fourth transistor, and the other of the source and the drain is electrically connected to the third wiring,
wherein a gate and a back gate of the sixth transistor are electrically connected to the first input terminal, one of a source and a drain is electrically connected to the first output terminal, and the other of the source and the drain is electrically connected to the third wiring,
wherein a gate and a back gate of the seventh transistor are electrically connected to the second input terminal, one of a source and a drain is electrically connected to the gate and the back gate of the second transistor, and the other of the source and the drain is electrically connected to the third wiring, and
wherein a gate and a back gate of the eighth transistor are electrically connected to the second input terminal, one of a source and a drain is electrically connected to the second output terminal, and the other of the source and the drain is electrically connected to the third wiring.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/599,439Filed 8 Mar 2024

Priority

JP 2018-08107520 Apr 2018

Published

24 Oct 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10D 86/60
Characterised by multiple TFTs: wherein the TFTs are in active matrices
H03K 19/00315
Modifications for increasing the reliability for protection: in field-effect transistor circuits
H03K 19/017
Modifications for accelerating switching: in field-effect transistor circuits
H03K 19/094
Using semiconductor devices: using field-effect transistors

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims16