Low power and area clock monitoring circuit using ring delay arrangement

An integrated circuit (IC), comprising:

• at least one processing subsystem;
• at least one clock monitoring circuit for monitoring a clock signal coupled to the at least one processing subsystem and a clock signal externally generated from the IC or a plurality of clock signals generated internal to the IC, wherein the at least one clock monitoring circuit comprises:
• two ring pulse generators, each configured to generate a train of pulses corresponding to a duration of respective phases of the clock signal;
• two n-bit counters, each connected to a respective one of the two ring pulse generators, configured to count a number of pulses in respective pulse trains generated by the two ring pulse generators wherein a count of number of pulses in each respective pulse train is indicative of a duration of the respective phases of the clock signal;
• a clock slow detection circuit (CSD) configured to assert a CSD signal when durations of subsequent phases of the clock signal lengthen;
• a clock fast detection (CFD) circuit configured to assert a CFD signal when durations of subsequent phases of the clock signal shorten;
• and
• a logic circuit configured to provide a clock abnormality detect (CAD) signal when either the CSD signal or the CFD signal is asserted.

A method of operating a clock monitoring circuit for monitoring a clock signal, comprising:

• generating a train of pulses corresponding to a duration of respective phases of the clock signal;
• counting a number of pulses in respective generated pulse trains, wherein the number of pulses in each respective pulse train is indicative of the duration of the respective phases of the clock signal;
• determining, using the number of pulses, when durations of subsequent phases of the clock signal lengthen;
• determining, using the number of pulses, when durations of the subsequent phases of the clock signal shorten;
• and
• providing a clock abnormality detect (CAD) signal when the clock signal either lengthens or shortens.

A method of manufacturing an integrated circuit (IC) for monitoring a clock signal, comprising forming:

• two ring pulse generators, each configured to generate a train of pulses corresponding to a duration of respective phases of a clock signal;
• two n-bit counters, each connected to a respective one of the two ring pulse generators, configured to count a number of pulses in respective pulse trains generated by the two ring pulse generators wherein a count of number of pulses in each respective pulse train is indicative of a duration of the respective phases of the clock signal;
• a clock slow detection (CSD) circuit configured to assert a CSD signal when durations of subsequent phases of the clock signal lengthen;
• a clock fast detection (CFD) circuit configured to assert a CFD signal when durations of subsequent phases of the clock signal shorten;
• and
• a logic circuit configured to provide a clock abnormality detect (CAD) signal when either the CSD signal or the CFD signal is asserted.

An autonomous machine, comprising:

• at least one processing subsystem;
• and
• at least one clock monitoring circuit for monitoring a clock signal coupled to the at least one processing subsystem and an externally generated clock signal or a plurality of internally generated clock signals, wherein the clock monitoring circuit comprises:
• two ring pulse generators, each configured to generate a train of pulses corresponding to a duration of respective phases of a clock signal;
• two n-bit counters, each connected to a respective one of the two ring pulse generators, configured to count a number of pulses in respective pulse trains generated by the two ring pulse generators wherein a count of number of pulses in each respective pulse train is indicative of a duration of the respective phases of the clock signal;
• a clock slow detection (CSD) circuit configured to assert a CSD signal when durations of subsequent phases of the clock signal lengthen;
• a clock fast detection circuit (CFD) configured to assert a CFD signal when durations of subsequent phases of the clock signal shorten;
• and
• a logic circuit configured to provide a clock abnormality detect (CAD) signal when either the CSD signal or the CFD signal is asserted.

A clock monitoring circuit for monitoring a clock signal, comprising:

• two ring pulse generators, each configured to generate a train of pulses corresponding to a duration of respective phases of the clock signal;
• separate n-bit counters, each connected to a respective one of the two ring pulse generators, configured to count a number of pulses in respective pulse trains generated by the two ring pulse generators, wherein a count of the number of pulses in each respective pulse train is indicative of a duration of the respective phases of the clock signal;
• and
• a logic circuit configured to provide a clock abnormality detect (CAD) signal when durations of subsequent phases of the clock signal lengthen or shorten according to the count of the number of the pulses.