Method for manufacturing superjunction trench gate mosfet

A method for manufacturing a superjunction trench gate MOSFET, wherein, comprising the following steps:

• S1, forming a trench gate in a first-type epitaxial layer on an upper side of a first-type substrate, forming a second-type bulk region in a surface layer of the first-type epitaxial layer, and performing first-type heavy doping implantation in a surface layer of the second-type bulk region to form a source end first-type implantation region, wherein a first type is an N type and a second type is a P type, or the first type is a P type and the second type is an N type;
• S2, forming a first dielectric layer on an upper surface of a wafer;
• S3, covering the upper surface of the wafer with a first mask layer, and performing etching, so as to form a gate region gate contact that communicates the trench gate with the first dielectric layer at the trench gate in a gate region, and at the same time, form a gate region source contact that communicates the source end first-type implantation region with the second-type bulk region between laterally adjacent trench gates in the gate region and form a source region source contact that communicates the source end first-type implantation region with the second-type bulk region between laterally adjacent trench gates in a source region;
• S4, performing second-type ion implantation, so as to form a source second-type doped pillar in the first-type epitaxial layer below each of the gate region source contact and the source region source contact, and at the same time, form a gate second-type doped pillar in the first-type epitaxial layer below the gate region gate contact;
• S5, removing the first mask layer, performing a contact metal process, and filling each contact with metal tungsten;
• S6, performing metal layer deposition to form a top metal layer on the upper surface of the wafer;
• S7, covering the top metal layer with a second mask layer, and performing etching, so as to remove the second mask layer and the top metal layer above the source region source contact and the trench gate of the source region, retain the second mask layer and the top metal layer above the trench gate of the gate region, and retain the second mask layer and the top metal layer above the gate region source contact;
• S8, performing etching to remove the metal tungsten in the source region source contact;
• S9, removing the second mask layer and depositing a second dielectric layer on the upper surface of the wafer.