Phase-locked loop (pll) with automatic loop bandwidth control
AssigneeQUALCOMM Incorporated
InventorAlessio SANTICCIOLI
Life of this patent
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Abstract
Certain aspects of the present disclosure generally relate to techniques and apparatus for jitter detection using time-based and/or voltage-based techniques. An example jitter detection circuit generally includes: a comparator having a first input coupled to an input of the jitter detection circuit; a first combiner having an input coupled to an output of the comparator; an accumulator having an input coupled to an output of the first combiner, an output of the accumulator being coupled to an output of the jitter detection circuit; and a digital-to-analog converter (DAC) having an input coupled to the output of the accumulator, an output of the DAC being coupled to a second input of the comparator.
Claims25
A jitter detection circuit, comprising:
- a comparator having a first input coupled to an input of the jitter detection circuit;
- a first combiner having an input coupled to an output of the comparator;
- an accumulator having an input coupled to an output of the first combiner, an output of the accumulator being coupled to an output of the jitter detection circuit;
- and
- a digital-to-analog converter (DAC) having an input coupled to the output of the accumulator, an output of the DAC being coupled to a second input of the comparator.
A jitter detection circuit, comprising:
- a first digital-to-time converter (DTC);
- a second DTC;
- a phase detector (PD) having a first input coupled to an output of the first DTC and a second input coupled to an output of the second DTC;
- a first combiner having an input coupled to an output of the PD;
- and
- an accumulator having an input coupled to an output of the first combiner, wherein an output of the accumulator is coupled to a first input of the first DTC and to a first input of the second DTC.
A method for signal processing, comprising:
- comparing, via a comparator, a phase detector (PD) output voltage and an analog jitter detection signal to yield a comparator output signal;
- subtracting, via a first combiner, a digital signal from the comparator output signal;
- accumulating, via an accumulator, an output signal from the first combiner to generate a first jitter detection signal;
- and
- generating, via a digital-to-analog converter (DAC), the analog jitter detection signal based on the first jitter detection signal.
A method for signal processing, comprising:
- generating, via a first digital-to-time converter (DTC), a first time-domain signal based on a reference signal and a first jitter detection signal;
- generating, via a second DTC, a second time-domain signal based on an oscillating signal and the first jitter detection signal;
- generating, via a phase detector (PD), a PD signal indicating a phase difference between the first time-domain signal and the second time-domain signal;
- subtracting, via a first combiner, a digital signal from the PD signal to generate a combiner signal;
- and
- generating, via an accumulator, the first jitter detection signal based on the combiner signal.
Dependencies are inferred from the claim text.