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US 2024/0322684 A1Published application
Power down circuit and power down method
AssigneeNanya Technology Corporation
InventorChih-Hang Chang
Life of this patent
Estimating the term…
Abstract
A power down circuit and a power down method are provided. The power down circuit includes a holding circuit and a comparator. The holding circuit is coupled to receive a first power signal. The holding circuit is configured to hold the first power signal to generate a second power signal. The comparator is coupled to the holding circuit. The comparator is configured to compare the first power signal and the second power signal to determine whether the first power signal is dropped to be lower than a first threshold voltage.
Claims11
A power down circuit, comprising:
- a holding circuit coupled to receive a first power signal, the holding circuit being configured to hold the first power signal to generate a second power signal;
- and
- a comparator coupled to the holding circuit, the comparator being configured to compare the first power signal and the second power signal to determine whether the first power signal is dropped to be lower than a first threshold voltage.
A power down method, comprising:
- holding a first power signal to generate a second power signal;
- and
- comparing the first power signal and the second power signal to generate a comparison result on determining whether the first power signal is dropped to be lower than a first threshold voltage.
Dependencies are inferred from the claim text.