Memory device
AssigneeKioxia Corporation
InventorManabu SATO
Life of this patent
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Abstract
A memory device includes a memory cell array including a block including a first transistor connected to a first select gate line, a second transistor connected to a second select gate line, and a plurality of memory cells connected in series between the first and second transistors and each connected to one corresponding word line of a plurality of word lines, and a row control circuit that outputs a control signal for setting the block to be in a selected state or an unselected state based on a result of decoding an address, stores information indicating whether the block is a non-defective block, and controls an electrical state of the second select gate line independently of the first select gate line based on the control signal and the information.
Claims20
A memory device comprising:
- a memory cell array including a block including:
- a first transistor connected to a first select gate line,
- a second transistor connected to a second select gate line, and
- a plurality of memory cells connected in series between the first transistor and the second transistor and each connected to one corresponding word line of a plurality of word lines;
- and
- a row control circuit configured to:
- output a first control signal for setting the block to be in a selected state or an unselected state based on a result of decoding an address,
- store information indicating whether the block is a non-defective block or a defective block, and
- control an electrical state of the second select gate line independently of the first select gate line based on the first control signal and the information.
A memory device comprising:
- a memory cell array including a block including:
- a first transistor connected to a first select gate line,
- a second transistor connected to a second select gate line, and
- a plurality of memory cells connected in series between the first transistor and the second transistor and each connected to one corresponding word line of a plurality of word lines;
- and
- a row control circuit including:
- a first control circuit configured to control an electrical state of the first select gate line based on a first control signal for setting the block to be in a selected state or an unselected state, and
- a second control circuit configured to control an electrical state of the second select gate line based on the first control signal and information indicating whether the block is a non-defective block or a defective block.
Dependencies are inferred from the claim text.