US 2024/0319964 A1 · LARGE NUMBER INTEGER ADDITION USING VECTOR ACCUMULATION

Abstract

A processor includes one or more processor cores configured to perform accumulate top (ACCT) and accumulate bottom (ACCB) instructions. To perform such instructions, at least one processor core of the processor includes an ACCT data path that adds a first portion of a block of data to a first lane of a set of lanes of a top accumulator and adds a carry-out bit to a second lane of the set of lanes of the top accumulator. Further, the at least one processor core includes an ACCB data path that adds a second portion of the block of data to a first lane of a set of lanes of a bottom accumulator and adds a carry-out bit to a second lane of the set of lanes of the bottom accumulator.

Claims20

Dependent claims

A processor comprising:

one or more processor cores, wherein a processor core of the one or more processor cores includes a first data path configured to:
add a first portion of a block of data to a first lane of a set of lanes of a first accumulator to produce a first sum and a first carry-out bit;
store the first sum in the first lane of the set of lanes of the first accumulator;
and
add the first carry-out bit to a second lane of the set of lanes of the first accumulator.

2 more elements

Dependencies are inferred from the claim text.

Large number integer addition using vector accumulation

Life of this patent

Large number integer addition using vector accumulation

Life of this patent

Abstract

Claims20