High-performance filter bank channelizers

A high-performance channelizer, comprising:

• an input commutator receiving and commutating an input signal;
• an M-path polyphaser filter in communication with the commutator;
• and an M-path inverse discrete Fourier transform module processing outputs of the polyphaser filter,
• wherein the M-path polyphaser filter introduces a plurality of phase rotations in a time domain resulting in a workload reduction for a processor on which the channelizer is implemented.

A resampling channelizer, comprising:

• a frequency division multiplex (FDM) commutator receiving and commutating an FDM input signal;
• an M/2-path input data buffer in communication with the FDM commutator;
• an M-path polyphaser filter in communication with the input data buffer;
• a circular output buffer in communication with the M-path polyphaser filter;
• an M-point inverse fast Fourier (IFFT) module in communication with the circular output buffer;
• and
• a time division multiplex (TDM) commutator in communication with the M-point IFFT module and generating a TDM output signal, wherein the M-path polyphaser filter is operated at a sample rate above fs/M.

A half-band filter, comprising:

• an upper filter path including even indices of a low-pass filter;
• a lower filter path including even symmetric filter coeeficients;
• a switch in communication with the upper and lower filter paths and switching an input signal between the upper and lower filter paths;
• and
• a mixer in communication with the upper and lower filter paths and mixing outputs of the upper and lower filter paths.

A cascaded half-band filter, comprising:

• an input commutator receiving and commutating an input signal;
• a first M-path filter in communication with the input commutator;
• a first M-point circular buffer in communication with the first M-path filter;
• a first M-point inverse fast Fourier transform (IFFT) module in communication with the first M-point circular buffer;
• a second M-point IFFT module in communication with the first IFFT module;
• a second M-point circular buffer in communication with the second M-point IFFT module;
• a second M-path filter in communication with the second M-point circular buffer;
• and
• an output commutator in communication with the second M-path filter and generating an output signal,
• wherein the input commutator, the first M-path filter, the first M-point circular buffer, and the first M-point IFFT module form an analysis channelizer, and the second M-point IFFT module, the second M-point circular buffer, the second M-path filter, and the output commutator form a synthesis channelizer, the analysis channelizer cascaded with the synthesis channelizer.