Buffer circuit having enhanced slew rate

A buffer circuit for generating an output voltage according to an input voltage, the buffer circuit comprising:

• an input stage configured to provide a first differential current to a load stage or receive a second differential current from the load stage based on a difference between the input voltage and the output voltage;
• the load stage configured to apply gate voltages to a first output transistor and a second output transistor of an output stage based on the first differential current or the second differential current;
• the output stage configured to regulate the output voltage based on the gate voltages applied to the first output transistor and the second output transistor;
• and
• a slew rate compensator configured to provide a source current to the load stage or receive a sink current from the load stage to regulate the gate voltages of the first output transistor and the second output transistor,
• wherein the slew rate compensator comprises:
• a first comparator, a second comparator connected to the first comparator, and a source follower configured to reduce the input voltage by a threshold voltage of a MOS transistor included in the source follower and provide the reduced input voltage to a gate terminal of the second comparator.

A method of controlling a buffer circuit, the method comprising:

• comparing an input voltage and an output voltage of the buffer circuit;
• providing a source current to a load stage or receiving a sink current from the load stage by a slew rate compensator based on a difference between the input voltage and the output voltage;
• flowing a first compensation current and a second compensation current through a first differential mirror circuit and a second differential mirror circuit of the load stage based on the source current and the sink current;
• increasing or decreasing gate voltages of a first output transistor and a second output transistor of an output stage based on the first compensation current and the second compensation current;
• and
• allowing the output voltage to follow a rising or falling transition of the input voltage based on an increase or decrease in the gate voltages of the first output transistor and the second output transistor,
• wherein the comparing of the input voltage and the output voltage further comprises:
• comparing the difference between the input voltage and the output voltage when the input voltage is in the rising transition;
• and
• reducing the input voltage by a threshold voltage of a MOS transistor included in a source follower, and comparing the reduced input voltage with the output voltage when the input voltage is in the falling transition.