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US 2024/0311083 A1Published application
Commutative 1ulp hardware multiplier
AssigneeIntel Corporation
InventorTheo Alan Drane
Life of this patent
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Abstract
Described herein is a truncated modified Booth multiplier that is commutative and accurate to 1 unit in the last place. In various embodiments, the truncated Booth multiplier is a radix-4 Booth multiplier or a radix-8 Booth multiplier. The truncated Booth multiplier can be included within integer, floating-point, or fixed-point units within a graphics processor or compute accelerator, including matrix accelerator units or tensor processors.
Claims20
A graphics processor comprising:
- a plurality of processing elements including a multiplier, the multiplier including a truncated Booth multiplier that is commutative and accurate to 1 unit in the last place (ulp), the truncated Booth multiplier including a multiplicand input, a multiplier input, first circuitry to apply a Booth encoding to the multiplicand input and the multiplier input, and second circuitry to sum partial products generated based on the Booth encoding of the multiplicand input and the multiplier input to generate a product.
A method comprising:
- configuring a logic design for a truncated Booth multiplier in which an array of partial products is generated based on a multiplicand input and a multiplier input, wherein k least significant columns of partial product bits are excluded from generation;
- adjusting the logic by configuring a fixed constant to be added to least significant columns of the array of partial products, the fixed constant to compensate at least in part on the excluded columns of partial product bits;
- inserting an additional bit into the partial product, the additional bit calculated based on selected bits of the multiplicand input and multiplier input, the additional bit to enable commutative operation of the Booth multiplier;
- configuring an array of adders to sum the array of partial products, the fixed constant, and the additional bit, to generate a product for output from the Booth multiplier;
- and
- synthesizing the logic design for implementation as a truncated commutable Booth multiplier that is accurate to 1 unit in the last place (ulp).
3 more elements
A multiplier circuit comprising:
- first circuitry to accept a multiplicand input and a multiplier input;
- second circuitry to apply a Booth encoding to the multiplicand input and the multiplier input;
- fourth circuitry to generate an array of binary partial products based on the Booth encoding of the multiplicand input and the multiplier input, the array of binary partial products excluding k least significant columns of partial products;
- and
- fifth circuitry to sum the binary array of partial products, a fixed constant value to compensate for excluded k least significant columns of partial products, and an additional bit calculated based on selected bits of the multiplicand input and the multiplier input, the fifth circuitry to generate a product for output, wherein the multiplier circuit is commutative and accurate to 1 unit in the last place (ulp).
2 more elements
Dependencies are inferred from the claim text.