Clock Frequency Limiter
AssigneeApple Inc.
InventorsJose A. Tierno, Ajay M. Rao
Life of this patent
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Abstract
A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit configured to generate an equalized signal, a clock generator circuit configured to generate a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit is configured to monitor a frequency of the clock signal and activate an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. In response to activation of the indication signal, the clock generator circuit is configured to set the frequency of the clock signal to a particular frequency.
Claims20
An apparatus, comprising:
- a front-end circuit configured to generate an equalized signal using a plurality of signals that encode a serial data stream that includes a plurality of data symbols;
- a clock generator circuit configured to generate a clock signal using a plurality of samples of the equalized signal;
- and
- a measurement circuit configured to:
- monitor a frequency of the clock signal;
- and
- in response to a determination that the frequency of the clock signal exceeds a threshold frequency, activate an indication signal, wherein the threshold frequency is set at a level that causes a response to a frequency runaway condition caused by interruption of the serial data stream;
- and
- wherein the clock generator circuit is further configured, in response to activation of the indication signal, to adjust the frequency of the clock signal to a particular frequency.
A method, comprising:
- receiving at least one signal via a communication link, wherein the at least one signal encodes a serial data stream that includes a plurality of data symbols;
- sampling the at least one signal at multiple points in time to generate a plurality of samples;
- generating a clock signal using the plurality of samples;
- monitoring a frequency of the clock signal;
- and
- in response to determining that the frequency of the clock signal exceeds a threshold frequency, setting the frequency of the clock signal to a particular frequency, wherein the threshold frequency is set at a level that causes response to a frequency runaway condition caused by interruption of the serial data stream.
An apparatus, comprising:
- a receiver circuit coupled to a communication link, wherein the receiver circuit is configured to:
- receive at least one signal that encodes a serial data stream that includes a plurality of data symbols;
- sample the at least one signal at multiple points in time to generate a plurality of samples;
- generate a clock signal using the plurality of samples;
- generate a plurality of recovered data symbols using the clock signal and the plurality of samples;
- monitor a frequency of the clock signal;
- and
- in response to a determination that the frequency of the clock signal exceeds a threshold frequency, set the frequency of clock signal to a particular frequency, wherein the threshold frequency is set at a level that causes response to a frequency runaway condition caused by interruption of the serial data stream;
- and
- a circuit block configured to perform one or more processing operations using the clock signal and the plurality of recovered data symbols.
Dependencies are inferred from the claim text.