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US 2024/0304265 A1Published application
Masking Techniques for Memory Applications
AssigneeArm Limited
InventorsEttore Amirante, Vivek Asthana, Yew Keong Chong, Jean-Christophe Vial
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Abstract
Various implementations described herein are related to a device including a bitcell having a bitcell layout with a first metal layer, a second metal layer and a via programming layer. The device may have a via marking layer provided in the bitcell layout for the bitcell, and the via marking layer controls optical proximity correction of the first metal layer and the second metal layer.
Claims20
A device comprising:
- a bitcell having a bitcell layout with a first metal layer, a second metal layer and a via programming layer;
- and
- a via marking layer provided in the bitcell layout for the bitcell,
- wherein the via marking layer controls optical proximity correction of the first metal layer and the second metal layer.
1 more element
A device comprising:
- a first metal layer provided in a bitcell layout for a bitcell with a first metal mask;
- a via programming layer provided in the bitcell layout for the bitcell with a single via programming mask;
- a second metal layer provided in the bitcell layout with a second metal mask;
- and
- a via marking layer provided in the bitcell layout,
- wherein the via marking layer controls optical proximity correction of the first metal layer and the second metal layer.
3 more elements
A method comprising:
- providing a bitcell layout for a bitcell having a first metal layer, a second metal layer and a via programming layer;
- and
- providing a via marking layer in the bitcell layout for the bitcell,
- controlling optical proximity correction of the first metal layer and the second metal layer with the via marking layer.
1 more element
Dependencies are inferred from the claim text.