Incremental delta modulation for analog to digital converter signal to noise ratio and linearity enhancement

An apparatus, comprising:

• a first circuit comprising capacitors;
• a second circuit configured to generate a first code using the first circuit;
• a third circuit configured to generate a number of codes using the first circuit;
• and
• a fourth circuit configured to select, from the capacitors, a different set of capacitors for each code of the number of codes;
• and
• a fifth circuit, wherein in response to a determination of an average of the number of codes, the fifth circuit adds the first code with the average to generate a second code.

An apparatus, comprising:

• a capacitive digital to analog converter (CDAC) circuit comprising a plurality of sets of capacitors;
• a first circuit configured to generate a first code based on a SAR operation;
• a second circuit configured to perform, using the CDAC circuit, a first number of cycles and generate a second number of codes, wherein the first number is equal to the second number;
• and
• a third circuit configured to select one or more capacitors from the plurality of sets of capacitors for each of the first number of cycles.