Compact frequency-locked loop architecture for digital clocking

A circuit for generating an oscillating signal, the circuit comprising:

• a frequency-locked loop (FLL) including a digital-to-analog converter (DAC), a discrete-time integrator having an input coupled to an output of the DAC, and a voltage-controlled oscillator (VCO) having a control input coupled to an output of the discrete-time integrator;
• a reference clock generator selectively coupled to one or more clock inputs of the FLL;
• and
• an oscillator selectively coupled to the one or more clock inputs of the FLL.

A method of signal generation, comprising:

• receiving, at an input of a counter, an output signal from a voltage-controlled oscillator (VCO) of a frequency-locked loop (FLL) circuit;
• determining, via the counter, a counter output signal representing a frequency of the output signal;
• determining, via a combiner, an error signal based on a difference between a target frequency and the frequency of the output signal;
• generating, via a digital-to-analog converter (DAC), an analog signal based on the error signal;
• generating, via a discrete-time integrator, a control voltage by integrating the analog signal;
• and
• controlling the VCO via the control voltage.

An apparatus for signal generation, comprising:

• means for determining a frequency indication signal representing a frequency of an output signal from a voltage-controlled oscillator (VCO) of a frequency-locked loop (FLL) circuit;
• means for determining an error signal based on a difference between a target frequency and the frequency of the output signal;
• means for generating an analog signal based on the error signal;
• and
• means for generating a control voltage, the means for generating the control voltage including means for integrating the analog signal in discrete time, the VCO being controlled via the control voltage.