Low-power flip flop circuit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPo-Chia LAI, Meng-Hung SHEN, Chi-Lin LIU, Stefan RUSU, Yan-Hao CHEN, Jerry Chang-Jui KAO
Life of this patent
Estimating the term…
Abstract
A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.
Claims20
A flip-flop circuit configured to latch an input signal to an output signal, comprising:
- a multiplexer configured to select either a data signal or a scan-in signal as the input signal in response to an enable signal;
- a first latch circuit having an input coupled to an output of the multiplexer;
- a second latch circuit coupled to the first latch circuit, wherein in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and wherein the first and second latch circuits each comprises at most two transistors configured to receive the clock signal;
- and
- a time-borrowing circuit coupled to the first latch circuit so as to delay the clock signal to the first latch circuit, and wherein the time-borrowing circuit does not delay the clock signal to the second latch circuit.
A flip-flop circuit configured to latch an input signal to an output signal, comprising:
- a multiplexer configured to select from at least two signals as the input signal;
- a first latch circuit coupled to the multiplexer;
- a second latch circuit coupled to the first latch circuit, wherein in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, wherein the first latch circuit includes a pair of cross-coupled OR-AND-Inverter (OAI) logic gates, and the second latch circuit includes a pair of cross-coupled AND-OR-Inverter (AOI) logic gates;
- and
- a time-borrowing circuit coupled to the first latch circuit so as to delay the clock signal to the first latch circuit, and wherein the time-borrowing circuit does not delay the clock signal to the second latch circuit.
A flip-flop circuit configured to latch an input signal to an output signal, comprising:
- a multiplexer configured to select either a data signal or a scan-in signal as the input signal in response to an enable signal;
- a first latch circuit having an input coupled to an output of the multiplexer;
- a second latch circuit coupled to the first latch circuit, wherein in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, wherein the first and second latch circuits each comprises at most two transistors configured to receive the clock signal, wherein the first latch circuit includes a first pair of logic gates and the second latch circuit includes a second pair of logic gates;
- a time-borrowing circuit coupled to the first latch circuit so as to delay the clock signal to the first latch circuit, and wherein the time-borrowing circuit does not delay the clock signal to the second latch circuit;
- and
- an inverter circuit, coupled to the first and second latch circuits, and configured to provide a logically inverted clock signal to the at most two transistors of the first latch circuit and the at most two transistors of the second latch circuit, respectively.
Dependencies are inferred from the claim text.