One-time programmable memory cell and method for managing the logic state of the memory cell
AssigneeSTMicroelectronics International N.V.
InventorPascal FORNARA
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Abstract
A memory cell is formed by a PIN diode having three contacts. A breakdown voltage is applied to break down a gate oxide arranged between a region of the PIN diode and a substrate region. The breakdown or non-breakdown state of the gate oxide is determined by applying a read voltage between the anode and the cathode of the diode and determining the value of the corresponding current flowing in the diode.
Claims21
An integrated memory device, comprising:
- a one-time programmable memory cell including a first semiconductor bar having a lower face and an upper face opposite the lower face, a first electrically isolating region located between a first zone of the lower face and a semiconductor region, and a second electrically isolating region thicker than the first electrically isolating region located between a second zone of the lower face and said semiconductor region;
- wherein the one-time programmable memory cell has a first logic state in the presence of a non-electrically broken down first electrically isolating region and a second logic state in the presence of an electrically broken down first electrically isolating region;
- a first circuit configured to apply a breakdown potential difference between the semiconductor region and the first semiconductor bar so as to break down the first electrically isolating region;
- and
- a second circuit configured to apply a read voltage between two locations of the upper face of the silicon bar and determine the value of the current flowing between the two locations so as to determine the logic state of the one-time programmable memory cell.
A method for managing the logic state of a one-time programmable memory cell, the one-time programmable memory cell including a first semiconductor bar having a lower face and an upper face opposite the lower face, a first electrically isolating region located between a first zone of the lower face and a semiconductor region, a second electrically isolating region thicker than the first electrically isolating region located between a second zone of the lower face and said semiconductor region, the method comprising:
- wherein the one-time programmable memory cell has a first logic state in the presence of a non-electrically broken down first electrically isolating region;
- wherein the one-time programmable memory cell has a second logic state in the presence of an electrically broken down first electrically isolating region;
- and
- breaking down the first electrically isolating region by applying a breakdown potential difference between the semiconductor region and the semiconductor bar.
A method for managing the logic state of a one-time programmable memory cell, the one-time programmable memory cell including a first semiconductor bar having a lower face and an upper face opposite the lower face, a first electrically isolating region located between a first zone of the lower face and a semiconductor region, a second electrically isolating region thicker than the first electrically isolating region located between a second zone of the lower face and said semiconductor region, the method comprising:
- wherein the one-time programmable memory cell has a first logic state in the presence of a non-electrically broken down first electrically isolating region;
- wherein the one-time programmable memory cell has a second logic state in the presence of an electrically broken down first electrically isolating region;
- and
- determining the logic state of the memory cell by applying a read voltage between two locations of the upper face of the silicon bar and determining the value of the current flowing between the two locations.
Dependencies are inferred from the claim text.