US 2024/0290827 A1 · INSULATED GATE BIPOLAR TRANSISTOR WITH SUPER JUNCTION STRUCTURE, AND PREPARATION METHOD THEREFOR

Abstract

Provided in the present invention are an insulated gate bipolar transistor with a super junction structure, and a preparation method therefor. The transistor comprises a drift region of a first conduction type, an epitaxial layer, a plurality of trenches arranged at intervals, filling layers of a second conduction type, gate electrode structures, a body region, a body contact region, a source region, an isolation dielectric layer and a source electrode conductive layer, wherein the epitaxial layer is located on an upper surface of the drift region; the filling layers and the gate electrode structures are sequentially arranged in the trenches from bottom to top; each gate electrode structure comprises a gate conductive layer, and a gate dielectric layer, which is located on inner walls of the trench and an upper surface of the filling layer and wrap side walls and a bottom face of the gate conductive layer; the body contact region and the source region are located on an upper surface layer of the body region and are adjacent to an upper surface of the body region; the isolation dielectric layer is provided with a contact hole, which penetrates the isolation dielectric layer and exposes the source region and the body contact region; and the source electrode conductive layer fills the contact hole and covers the isolation dielectric layer. In the present invention, the filling layer is formed at the bottom of each trench so as to shield the overlapping area between the bottom of the trench and the drift region, thereby reducing gate electrode charges Qgc.

Claims15

Dependent claims

A method for manufacturing an insulated gate bipolar transistor with a super junction structure, comprising:

providing a first conductive type substrate to form a first conductive type drift region, and forming a first conductive type epitaxial layer on an upper surface of the substrate, a doping concentration of the epitaxial layer being higher than a doping concentration of the substrate;
forming a plurality of trenches spaced in the epitaxial layer, and forming a second conductive type filling layer in a trench, an upper surface of the filling layer being lower than a top surface of the epitaxial layer;
forming a gate dielectric layer on an inner wall of the trench and the upper surface of the filling layer, and forming a gate conductive layer in the trench with, a side wall and a bottom surface of the gate conductive layer being wrapped by the gate dielectric layer, an upper surface of the gate conductive layer being lower than the top surface of the epitaxial layer;
forming a second conductive type body region in an upper surface layer of the epitaxial layer on both sides of the trench, forming a second conductive type body contact region and a first conductive type source region adjacent to each other in an upper surface layer of the body region, and forming an isolation dielectric layer covering the upper surface of the epitaxial layer and the upper surface of the gate conductive layer;
and
forming a contact hole passing through the isolation dielectric layer to simultaneously expose the source region and the body contact region, and forming a source conductive layer filling the contact hole and covering the isolation dielectric layer.

3 more elements

An insulated gate bipolar transistor with a super junction structure, comprising:

a drift region;
an epitaxial layer located on an upper surface of the drift region, a doping concentration of the epitaxial layer being higher than a doping concentration of the substrate;
a plurality of trenches spaced which are located in the epitaxial layer;
a second conductive type filling layer and a gate structure sequentially arranged in the trench from bottom to top, wherein the gate structure comprises a gate dielectric layer and a gate conductive layer, and the gate dielectric layer is located on an inner wall of a trench and an upper surface of the filling layer and wraps a side wall and a bottom surface of the gate conductive layer;
a second conductive type body region located in an upper surface layer of the epitaxial layer on both sides of the trench;
a second conductive type body contact region and a first conductive type source region adjacent to each other located in an upper surface layer of the body region;
an isolation dielectric layer covering an upper surface of the source region and an upper surface of the gate conductive layer, wherein a contact hole passing through the isolation dielectric layer is provided in the isolation dielectric layer, and the contact hole simultaneously exposes the source region and the body contact region;
and
a source conductive layer filling the contact hole and covering the isolation dielectric layer.

6 more elements

Dependencies are inferred from the claim text.

Insulated gate bipolar transistor with super junction structure, and preparation method therefor

Life of this patent

Insulated gate bipolar transistor with super junction structure, and preparation method therefor

Life of this patent

Abstract

Claims15