Ggnmos transistor structure, esd protection device and circuit

A GGNMOS transistor structure, comprising:

• a P-type substrate;
• a first N-potential well, a P-potential well, and a second N-potential well that are adjacent and horizontally arranged on the P-type substrate in sequence;
• a first P-type heavily doped region arranged above the first N-potential well;
• a first N-type heavily doped region arranged above the first N-potential well, wherein an insulation structure is arranged between the first N-type heavily doped region and the first P-type heavily doped region;
• a second P-type heavily doped region arranged above the P-potential well, wherein an insulation structure is arranged between the second P-type heavily doped region and the first N-type heavily doped region;
• a second N-type heavily doped region arranged above the P-potential well, wherein an insulation structure is arranged between the second N-type heavily doped region and the second P-type heavily doped region;
• a third N-type heavily doped region arranged above a boundary between the P-potential well and the second N-potential well;
• a fourth N-type heavily doped region arranged above the second N-potential well, wherein an insulation structure is arranged between the fourth N-type heavily doped region and the third N-type heavily doped region;
• and
• a gate structure arranged on an upper surface of the P-potential well between the third N-type heavily doped region and the second N-type heavily doped region,
• wherein the first P-type heavily doped region, the first N-type heavily doped region, and the fourth N-type heavily doped region are connected to a positive electrode, and the second P-type heavily doped region, the second N-type heavily doped region, and the gate structure are connected to a negative electrode.