Nonvolatile semiconductor memory device
AssigneeKioxia Corporation
InventorTakashi MAEDA
Life of this patent
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Abstract
When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the 10 selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.
Claims21
(canceled)
A memory device, comprising:
- a plurality of first memory cells connected in series;
- a plurality of second memory cells connected in series;
- a first group of source side selective transistors electrically connected to the first memory cells, and including a first transistor and a second transistor connected in series;
- a second group of source side selective transistors electrically connected to the second memory cells, and including a third transistor and a fourth transistor;
- a source line electrically connected to the plurality of first memory cells via the first group of source side selective transistors, electrically connected to the plurality of second memory cells via the second group of source side selective transistors, and the source line positioned above a substrate;
- a plurality of first word lines electrically connected to gates of the first memory cells;
- a plurality of second word lines electrically connected to gates of the second memory cells;
- a first source side select gate line electrically connected to a gate of the first transistor;
- a second source side select gate line electrically connected to a gate of the second transistor;
- a third source side select gate line electrically connected to a gate of the third transistor;
- and
- a fourth source side select gate line electrically connected to a gate of the fourth transistor, wherein
- the first source side select gate line and the second source side select gate line are electrically disconnected from each other and capable to apply a voltage independently, and
- the third source side select gate line and the fourth source side select gate line are electrically disconnected from each other and capable to apply a voltage independently.
Dependencies are inferred from the claim text.