In-memory associative processing for vectors

A method at a memory device, comprising:

• reading, from a first plane of a first memory tile, data representative of a first set of contiguous bits of a first vector;
• reading, from the first plane of the first memory tile, data representative of a first set of contiguous bits of a second vector, the first set of contiguous bits of the second vector having same bit positions as the first set of contiguous bits of the first vector;
• determining an arithmetic output bit that is based on comparing the first set of contiguous bits of the first vector and the first set of contiguous bits of the second vector with bits of a truth table that indicates results of a computational operation for various combinations of logic values;
• and
• communicating the arithmetic output bit to a second plane based on the second plane storing a second set of contiguous bits, of the first vector, with bit positions that are contiguous with the bit positions of the first set of contiguous bits of the first vector and storing a second set of contiguous bits, of the second vector, with bit positions that are contiguous with the bit positions of the first set of contiguous bits of the second vector.

A memory device, comprising:

• a memory die comprising a first memory tile and a second memory tile each comprising a plurality of planes, wherein each plane comprises a respective array of content-addressable memory cells;
• and
• one or more controllers coupled with the memory die and configured to cause the memory device to:
• read, from a first plane of the first memory tile, data representative of a first set of contiguous bits of a first vector;
• read, from the first plane of the first memory tile, data representative of a first set of contiguous bits of a second vector, the first set of contiguous bits of the second vector having same bit positions as the first set of contiguous bits of the first vector;
• determine an arithmetic output bit that is based on comparing the first set of contiguous bits of the first vector and the first set of contiguous bits of the second vector with bits of a truth table that indicates results of a computational operation for various combinations of logic values;
• and
• communicate the arithmetic output bit to a second plane based on the second plane storing a second set of contiguous bits, of the first vector, with bit positions that are contiguous with the bit positions of the first set of contiguous bits of the first vector and storing a second set of contiguous bits, of the second vector, with bit positions that are contiguous with the bit positions of the first set of contiguous bits of the second vector.

A memory die, comprising:

• a first memory tile of content-addressable memory cells;
• and
• a second memory tile of content-addressable memory cells, wherein the memory die is configured to:
• read, from a first plane of the first memory tile, data representative of a first set of contiguous bits of a first vector;
• read, from the first plane of the first memory tile, data representative of a first set of contiguous bits of a second vector, the first set of contiguous bits of the second vector having same bit positions as the first set of contiguous bits of the first vector;
• determining an arithmetic output bit that is based on comparing the first set of contiguous bits of the first vector and the first set of contiguous bits of the second vector with bits of a truth table that indicates results of a computational operation for various combinations of logic values;
• and
• communicating the arithmetic output bit to a second plane, of the first memory tile or the second memory tile, based on the second plane storing a second set of contiguous bits, of the first vector, with bit positions that are contiguous with the bit positions of the first set of contiguous bits of the first vector and storing a second set of contiguous bits, of the second vector, with bit positions that are contiguous with the bit positions of the first set of contiguous bits of the second vector.