Charge pumps, logic circuits including charge pumps, logic devices including logic circuits, and methods of operating logic circuits
AssigneeGlobalFoundries U.S. Inc.
InventorsSantosh SHARMA, Mei Yu Soh
Life of this patent
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Abstract
A GaN logic circuit may include an input node receiving an input voltage, a first pull up transistor pulling up an output voltage in response to the input voltage, and a first depletion mode transistor having a first gate to which a first gate voltage is applied and a second gate to which a second gate voltage is applied. The first depletion mode transistor may control the first pull up transistor in response to a gate voltage difference between the first gate voltage and the second gate voltage. The logic device may further include a capacitor having a first end coupled to the first depletion mode transistor and a second end coupled to the first pull up transistor.
Claims20
A charge pump for a GaN logic circuit, comprising:
- a first transistor configured to pull up an output voltage in response to an input voltage;
- and
- a second transistor having a first gate, a second gate, and an output terminal coupled to a gate of the first transistor.
A GaN logic circuit, comprising:
- an input node configured to receive an input voltage;
- a first pull up transistor configured to pull up an output voltage in response to the input voltage;
- a first depletion mode transistor having a first gate to which a first gate voltage is applied and a second gate to which a second gate voltage is applied, the first depletion mode transistor configured to control the first pull up transistor in response to a gate voltage difference between the first gate voltage and the second gate voltage;
- and
- a capacitor having a first end coupled to the first depletion mode transistor and a second end coupled to the first pull up transistor.
A logic device, comprising:
- a logic gate configured to receive a pair of input signals and performs a logic operation on the received input signals to generate an intermediate signal;
- and
- a GaN inverter configured to receive the intermediate signal and generate an output signal, the inverter comprising:
- an input node configured to receive the intermediate signal;
- a pull up transistor configured to pull up the output signal in response to the intermediate signal;
- a depletion mode transistor having a first gate to which a first gate voltage applies and a second gate to which a second gate voltage applies, the depletion mode transistor configured to control the pull up transistor in response to a gate voltage difference between the first gate voltage and the second gate voltage;
- and
- a capacitor having a first end coupled to the depletion mode transistor and a second end coupled to the pull up transistor.
Dependencies are inferred from the claim text.