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US 2024/0268108 A1Published application
V-nand stacks with dipole regions
AssigneeApplied Materials, Inc.
InventorsYong Yang, Jacqueline S. Wrench, Yixiong Yang, Pradeep K. Subrahmanyan, Srinivas Gandikota
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Abstract
A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.
Claims14
A memory device comprising:
- a stack of alternating silicon oxide layers and wordline layers;
- and
- each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal.
A memory stack on a substrate comprising:
- a plurality of alternating silicon oxide layers and wordline layers on the substrate;
- a plurality of memory holes through the thicknesses of at least some of the alternating silicon oxide layers and wordline layers;
- and
- each wordline layer comprising:
- a gate oxide layer including one or more dipole regions, a gate metal fill layer, and optionally a barrier layer between the gate oxide layer and the gate metal fill layer, wherein the dipole regions are adjacent to each silicon oxide layer and portions of the memory holes, the dipole regions comprising:
- a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of and a dipole metal, wherein the dipole metal comprises an electronegativity that is greater than an electronegativity of a metal of the gate metal oxide layer.
3 more elements
Dependencies are inferred from the claim text.