Image sensor with stacked ccd and cmos architecture

An image sensor, comprising:

• a pixel array on a first substrate and having at least one column of image sensing pixels, wherein the at least one column of pixels includes at least a first pixel having a first gate over a semiconductor layer and a second pixel having a second gate over the semiconductor layer, wherein the first gate partially overlaps with the second gate;
• a conductive structure coupled to at least one pixel of the column of pixels;
• a readout circuit coupled to the conductive structure and on a second substrate different from the first substrate;
• a column amplifier coupled to the readout circuit;
• an analog-to-digital converter (ADC) coupled to the column amplifier;
• and
• a processor coupled to the ADC.

An image sensor, comprising:

• a first substrate having an array of image sensing pixels, wherein the array of image sensing pixels comprises a first pixel having a first gate and an adjacent second pixel having a second gate, and wherein the first gate partially overlaps with the second gate;
• a second substrate having a readout circuit that comprises one or more metal oxide semiconductor (MOS) devices;
• and
• a conductive structure that contacts at least a portion of the first substrate and at least a portion of the second substrate, wherein the conductive contact is coupled to an image sensing pixel of the array of image sensing pixels and is coupled to the readout circuit.