Semiconductor device having device element structures with pn junction formed in active region and voltage withstanding rings formed in periphery region surrounding the active region and method of manufacturing semiconductor device

A semiconductor device having an active region through which a main current flows and a termination region surrounding a periphery of the active region, the semiconductor device comprising:

• a semiconductor substrate containing a semiconductor having a bandgap wider than a bandgap of silicon, the semiconductor substrate having a first main surface and a second main surface opposite to each other, the semiconductor substrate including a first-conductivity-type epitaxial layer that forms the first main surface of the semiconductor substrate;
• a first semiconductor region of a first conductivity type, provided in the semiconductor substrate;
• a second semiconductor region of a second conductivity type, selectivity provided in the semiconductor substrate in the active region, between the first main surface of the semiconductor substrate and the first semiconductor region;
• a device element structure formed in the semiconductor substrate in the active region, the device element structure having a pn junction between the second semiconductor region and the first semiconductor region;
• a first electrode electrically connected to the second semiconductor region;
• a second electrode provided on the second main surface of the semiconductor substrate;
• and
• a plurality of second-conductivity-type voltage withstanding regions each selectively provided in the semiconductor substrate in the termination region, between the first main surface of the semiconductor substrate and the first semiconductor region, separate from the device element structure, the plurality of second-conductivity-type voltage withstanding regions concentrically surrounding the periphery of the active region to form concentric circles in a plan view of the semiconductor device, and being each provided separate from one another in a radial direction of the concentric circles, wherein
• the device element structure includes:
• a plurality of third semiconductor regions of the first conductivity type, selectively provided in the semiconductor substrate, between the first main surface of the semiconductor substrate and the second semiconductor region;
• a plurality of trenches penetrating through the plurality of third semiconductor regions and the second semiconductor region, and reaching the first semiconductor region;
• a plurality of gate electrodes that are respectively provided in the plurality of trenches via a respective one of a plurality of gate insulating films;
• and
• a plurality of fourth semiconductor regions of the second conductivity type, selectively provided in the semiconductor substrate, between the first main surface of the semiconductor substrate and the second semiconductor region, the plurality of fourth semiconductor regions having an impurity concentration higher than an impurity concentration of the second semiconductor region,
• the first main surface of the semiconductor substrate is a flat surface spanning both the active region and the termination region,
• the second semiconductor region and the plurality of second-conductivity-type voltage withstanding regions are impurity diffusion regions, each of which is selectively provided in a first portion of the first-conductivity-type epitaxial layer,
• the first semiconductor region is a second portion of the first-conductivity-type epitaxial layer excluding the first portion of the first-conductivity-type epitaxial layer, the second portion including regions, each of which is provided between a corresponding two of the plurality of second-conductivity-type voltage withstanding regions that are adjacent to each other and reaches the first main surface of the semiconductor substrate,
• each of the plurality of second-conductivity-type voltage withstanding regions is formed by a plurality of second-conductivity-type regions that are stacked upon one another in a depth direction orthogonal to the first main surface of the semiconductor substrate,
• the second semiconductor region includes a lower second semiconductor region provided below each of the plurality of fourth semiconductor regions in the depth direction, and an upper second semiconductor region provided on the lower second semiconductor region below the plurality of third semiconductor region in the depth direction, an impurity concentration of the lower second semiconductor region being lower than impurity concentrations of the upper second semiconductor region and at least a portion of each of the plurality of second-conductivity-type voltage withstanding regions.