Semiconductor device
AssigneeNuvoton Technology Corporation Japan
InventorYusuke KANDA
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer; a source electrode and a drain electrode; and a gate electrode that is spaced apart from the source electrode and the drain electrode, and is in contact with the second nitride semiconductor layer. The gate electrode includes: a first barrier layer that includes TaN, has a layer thickness of Z1, and forms a Schottky junction with the second nitride semiconductor layer; a second barrier layer that is disposed above and in contact with the first barrier layer, includes TiN or WN, and has a layer thickness of Z2; and a wiring layer disposed above and in contact with the second barrier layer. In the semiconductor device, 200 nm≥Z1+Z2≥50 nm, Z1<Z2, and 50 nm>Z1>3 nm are satisfied.
Claims20
A semiconductor device comprising:
- a substrate;
- a first nitride semiconductor layer disposed above the substrate;
- a second nitride semiconductor layer disposed above the first nitride semiconductor layer, the second nitride semiconductor layer having a larger band gap than a band gap of the first nitride semiconductor layer;
- a first insulating layer disposed above the second nitride semiconductor layer;
- a source electrode and a drain electrode spaced apart from each other, the source electrode and the drain electrode each penetrating through the first insulating layer and being electrically connected to the first nitride semiconductor layer;
- an opening portion provided in the first insulating layer between the source electrode and the drain electrode to expose the second nitride semiconductor layer;
- and
- a gate electrode spaced apart from the source electrode and the drain electrode, the gate electrode being in contact with the second nitride semiconductor layer in the opening portion, wherein
- the gate electrode includes:
- a first barrier layer including TaN and having a layer thickness of Z1, the first barrier layer being a layer that forms a Schottky junction with the second nitride semiconductor layer;
- a second barrier layer disposed above and in contact with the first barrier layer, the second barrier layer including TiN or WN and having a layer thickness of Z2;
- and
- a wiring layer disposed above and in contact with the second barrier layer, and 200 nm≥Z1+Z2≥50 nm, Z1<Z2, and 50 nm>Z1>3 nm are satisfied.
Dependencies are inferred from the claim text.