Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first vertical arrangement of nanowires and a second vertical arrangement of nanowires, the first vertical arrangement of nanowires having a greater number of nanowires than the second vertical arrangement of nanowires, the first vertical arrangement of nanowires having an uppermost nanowire co-planar with an uppermost nanowire of the second vertical arrangement of nanowires, and the first vertical arrangement of nanowires having a bottommost nanowire below a bottommost nanowire of the second vertical arrangement of nanowires, wherein the first vertical arrangement of nanowires is over a first fin, the first fin having an uppermost surface, and the second vertical arrangement of nanowires is over a second fin, the second fin having an uppermost surface below the uppermost surface of the first fin, wherein the bottommost nanowire of the first vertical arrangement of nanowires is vertically spaced apart from the first fin by a first distance, and wherein the bottommost nanowire of the second vertical arrangement of nanowires is vertically spaced apart from the second fin by a second distance, the second distance greater than the first distance;
• a first gate stack over the first vertical arrangement of nanowires;
• and
• a second gate stack over the second vertical arrangement of nanowires.