Hybrid bonding with uniform pattern density
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSzu-Ying Chen, Dun-Nian Yaung
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Abstract
A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.
Claims20
An integrated circuit structure comprising:
- a first chip comprising:
- a first semiconductor substrate comprising a bottom surface;
- a surface dielectric layer comprising a top surface, wherein the top surface is higher than the bottom surface of the first semiconductor substrate;
- a first plurality of dielectric layers underlying the first semiconductor substrate and the surface dielectric layer, wherein the first plurality of dielectric layers comprise a first portion directly underlying and overlapped by the first semiconductor substrate and a second portion directly underlying and overlapped by the surface dielectric layer;
- and
- a first plurality of metal pads in a bottom dielectric layer of the first plurality of dielectric layers, wherein the first plurality of metal pads are distributed with substantially uniform spacings, and wherein the first plurality of metal pads comprise active metal pads and dummy metal pads;
- and
- a second chip underlying and bonded to the first chip, wherein the second chip comprises:
- a second plurality of metal pads physically bonded to the first plurality of metal pad with a one-to-one correspondence.
An integrated circuit structure comprising:
- a first chip comprising:
- a semiconductor substrate;
- a plurality of dielectric layers underlying the semiconductor substrate, wherein the plurality of dielectric layers extend laterally beyond edges of the semiconductor substrate, and wherein the plurality of dielectric layers comprise a bottom dielectric layer;
- image sensors in the semiconductor substrate;
- a plurality of wire bond structures comprising portions higher than a bottom surface of the semiconductor substrate, and lower than a top surface of the semiconductor substrate;
- and
- a first plurality of metal pads in the bottom dielectric layer and comprising active metal pads and dummy metal pads, wherein the first plurality of metal pads comprise first metal pads directly underlying the semiconductor substrate, and second metal pads directly underlying a chip area occupied by the plurality of wire bond structures;
- and
- a second chip underlying the first chip, wherein the second chip comprises a second plurality of metal pads bonding to the first plurality of metal pads.
An integrated circuit structure comprising:
- a first chip comprising:
- a semiconductor substrate comprising a first edge and a second edge, wherein the first edge and the second edge are opposite edges of the semiconductor substrate;
- a first dielectric layer underlying the semiconductor substrate, wherein the first dielectric layer comprises:
- a first portion underlying and overlapped by the semiconductor substrate;
- and
- a second portion laterally beyond the first edge and the second edge;
- a first plurality of metal pads distributed substantially uniformly, wherein the first plurality of metal pads are in the first portion and the second portion of the first dielectric layer;
- and
- a second chip comprising:
- a second plurality of metal pads joined to the first plurality of metal pads.
Dependencies are inferred from the claim text.