Semiconductor memory device and manufacturing method of semiconductor memory device
AssigneeSK hynix Inc.
InventorNam Jae LEE
Life of this patent
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Abstract
There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes: a peripheral circuit layer; a bonding structure disposed on the peripheral circuit layer; a channel structure disposed on the bonding structure; a first gate contact structure including a first vertical part penetrating the bonding structure and a first horizontal part intersecting with the first vertical part and extending from the first vertical part; and a first gate conductive pattern in contact with a sidewall of the first horizontal part, the first gate conductive pattern being spaced apart from the first vertical part, the first gate conductive pattern extending to surround the channel structure.
Claims15
A method of manufacturing a semiconductor memory device, the method comprising:
- forming a step structure over a sacrificial substrate, wherein the step structure includes first material layers stacked to be spaced apart from each other while surrounding a channel structure, a second material layer surrounding the channel structure between the first material layers, and a gap fill pattern disposed on a sidewall of the second material layer between the first material layers;
- forming a gap fill insulating layer covering the step structure;
- forming a contact hole intersecting the gap fill pattern, wherein the contact hole penetrates the gap fill insulating layer, the first material layers, and the second material layer;
- forming a spacer insulating layer on a sidewall of the contact hole;
- forming a sacrificial pillar to fill a central region of the contact hole, which is opened by the spacer insulating layer;
- forming a first insulating layer extending to overlap with the sacrificial pillar and the gap fill insulating layer;
- bonding the first insulating layer to a second insulating layer covering a peripheral circuit layer;
- and
- replacing the sacrificial pillar and the gap fill pattern with a gate contact structure penetrating the first insulating layer and the second insulating layer.
A method of manufacturing a semiconductor memory device, the method comprising:
- forming a stack structure over a sacrificial substrate, wherein the stack structure includes first material layers and second material layers, which are alternately stacked;
- forming a contact hole penetrating the stack structure;
- etching a portion of each of the second material layers through the contact hole to open gaps between the first material layers;
- forming a spacer insulating layer filling the gaps, wherein the spacer insulating layer extends along a sidewall of the contact hole;
- forming a sacrificial pillar to fill a central region of the contact hole, which is opened by the spacer insulating layer;
- forming a first insulating layer extending to overlap with the sacrificial pillar and the stack structure;
- bonding a second insulating layer covering a peripheral circuit layer to the first insulating layer;
- and
- replacing the sacrificial pillar with a vertical contact structure penetrating the first insulating layer and the second insulating layer.
Dependencies are inferred from the claim text.